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Old 22nd January 2013, 12:43 PM   #391
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Quote:
Originally Posted by steph_tsf View Post
Can somebody advise me how to assign the USICs on the Infineon XMC4500 Relax Lite kit ?
Sorry, don't understand what you mean with "assign the USICs". Anyway, each of six USIC channels, two per each independent USIC (3x2=6) have independent address space, see 17.11.1 Address Map

Table 17-20 Registers Address Space

Module Base Address End Address
---------------- ---------------- ---------------
USIC0_CH0 40030000H 400301FFH
USIC0_CH1 40030200H 400303FFH
USIC1_CH0 48020000H 480201FFH
USIC1_CH1 48020200H 480203FFH
USIC2_CH0 48024000H 480241FFH
USIC2_CH1 48024200H 480243FFH

So you can connect your I2S_data_in to for an example USIC0_CH0.DX0A input, or any of these:

Table 17-22 USIC Module 0 Channel 0 Interconnects
Input/Output
I/O Connected To Description
USIC0_CH0.DX0A I P1.5 Shift data input
USIC0_CH0.DX0B I P1.4 Shift data input
USIC0_CH0.DX0C I P4.7 Shift data input
USIC0_CH0.DX0D I P5.0 Shift data input

(there are more input "pins" like loopback and XTAL but not very useful)

Likewise output goes to output USIC0_CH0.DOUT0 (multiple locations), or generally to USICn_CHy.DOUT0 where n=0,1,2 and y=0,1.
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Old 22nd January 2013, 06:01 PM   #392
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@mhelin, thanks a zillion for helping me!
What do you think about the following pin multiplexing approaches?

- ALT2 looks nice for four bidirectional I2S, featuring all control signals, however I don't know if I2C and SPI can be added (for the WM8580, one I2C is needed).
- Within the ALT2 scheme, is it allowed to configure U1C1 as I2C instead of I2S? This way there are three I2S and one I2C.
- HWO0 looks nice for six communication channels, however all control signals seem to be missing, and we need them. How to add them?

Is is allowed to blend "ALT2" and "HWO0" perhaps ?

************************************************** ***
XMC4500 : ALT2 = four I2S_out plus four I2S_in with all control signals
************************************************** ***

U0C0
****
DOUT0 P1.5 I2S out
DX0B P1.4 I2S in
SEL0 P1.0 Frame Sync
SCLK P1.1 Shift Clock
MCLK P1.2 High Frequency Clock (not needed with WM8580 or WM8581)

U0C1
****
DOUT0 P3.13 I2S out
DX0D P3.12 I2S in (not needed with WM8580 or WM8581)
SEL0 P6.1 Frame Sync
SCLK P6.2 Shift Clock
MCLK P6.5 High Frequency Clock (not needed with WM8580 or WM8581)

U1C0
****
DOUT0 P0.5 I2S out
DX0A P0.4 I2S in (not needed with WM8580 or WM8581)
SEL0 P5.9 Frame Sync
SCLK P5.8 Shift Clock
MCLK P5.10 High Frequency Clock (not needed with WM8580 or WM8581)

U1C1
****
DOUT0 P0.1 I2S out (only with WM8581)
DX0D P0.0 I2S in (not needed with WM8580 or WM8581)
SEL0 P0.9 Frame Sync
SCLK P0.10 Shift Clock
MCLK P4.1 High Frequency Clock (not needed with WM8580 or WM8581)

U2C0
****
Question : is it available as I2C (dedicated WM8580/WM8581 control bus) ?

U2C1
****
Question : is it available as SPI (general control bus) ?



************************************************** *****
XMC4500: HWO0 = six I2S_out plus six I2S_in without any control signal
************************************************** *****

U0C0
****
DOUT0 P1.5 I2S out
DX0B P1.4 I2S in

U0C1
****
DOUT0 P3.13 I2S out
DX0D P3.12 I2S in (not needed with WM8580 or WM8581)

U1C0
****
DOUT0 P0.5 I2S out
DX0A P0.4 I2S in (not needed with WM8580 or WM8581)

U1C1
****
DOUT0 P3.15 I2S out
DX0B P3.14 I2S in (not needed with WM8580 or WM8581)

U2C0
****
DOUT0 P5.0 Ideally, this would be a I2C bus (as dedicated WM8580/WM8581 control bus)
DX0A P5.1

U2C1
****
DOUT0 P4.7 Ideally, this would be a SPI (as general control bus)
DX0A P3.5 (consumes SDMMC.CMD_OUT)

Question : for all six serial interfaces, how to get the control signals SEL0 and SCLK ?

Infineon is advertising "6 x I2S".
Do they mean "6 x full duplex I2S" ?
Configuring all USICs as I2S, is it possible to sync all six I2S on a common Frame_Sync and Shift_Clock ?

Last edited by steph_tsf; 22nd January 2013 at 06:13 PM.
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Old 22nd January 2013, 07:09 PM   #393
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I haven't studied output pinning but I think you can select mode for each pin separately. I would prefer ALT modes because I2S doesn't need HW modes (don't know which interface or protocol requires them but some will). Input pinning, well it's quite free. Regarding the channel protocols you control them via CCR.MODE register, thats Channel Control Register, so I assume you can select different protocol for each channel if needed:

------
CCR

MODE [3:0] rw Operating Mode
This bit field selects the protocol for this USIC
channel. Selecting a protocol that is not available (see
register CCFG) or a reserved combination disables
the USIC channel. When switching between two
protocols, the USIC channel has to be disabled
before selecting a new protocol. In this case, registers
PCR and PSR have to be cleared or updated by
software.
0H The USIC channel is disabled. All protocolrelated
state machines are set to an idle state.
1H The SSC (SPI) protocol is selected.
2H The ASC (SCI, UART) protocol is selected.
3H The IIS protocol is selected.
4H The IIC protocol is selected.
Other bit combinations are reserved.
---

It's good idea to think which serial protocols are needed first. I2C or SPI for DAC/CODEC control, yes. Then how about UART, do you want to update the biquads using simple UART terminal? How about USB, could it be used for downloading filter coefficients? Does USB need isolator to avoid ground loops (off topic but good question if you are planning to use USB)?

If one I2S is master then other I2S channels can be slaves and for sure can be synched (though may need external links). There may be other ways but I'm not sure. I haven't ordered those kits yet because I'd like order them from Mouser with other stuff to fullfil the 65 EUR limit to get free delivery at least (must pay the VAT unfortunately here in Europe). LPC4300 looks better because of the speed and SGPIO, though there may be some hidden things preventing good performance. For an example the XMC4500 does have internal cache which is excellent thing at high clock speeds. I don't know if anyone has tried overclocking them yet (if that's possible), but at least the performance wouldn't be lacking because of the need to use wait states to read program code or data from slow flash. Anyway the XMC part looks good, it seems to be better for xover application than STM32F4 because of the USIC's. The DAVE might make programming easier when it gets I2S support - it might be good idea to download the software and try to use it if not for I2S then for I2C or SPI, it might be the generated code is easy to change to use I2S protocol by changing just the CCR.MODE setting and pinning.

Then there are at least two ways to handle the I/O buffering - either use FIFO or DMA. FIFO is simpler to start, but it's difficult to evaluate the performance. Maybe you can enable some GPIO pins and output some strobes and look with oscilloscope how long the subroutine takes time.
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Old 22nd January 2013, 07:18 PM   #394
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This pdf mentions XMC4700 chip with 180 MHz clock, 512kB RAM, 2Mb flash and 6 kB cache:
http://www.hardwareconference.nl/fil...ngo_Skuras.pdf

Now that would be something, hopefully there will be new Relax Lite kit with that chip (it might be possible they are pin-compatible).

E: The XMC4700 is out Q1 2014 so no reason to wait for it now.

Last edited by mhelin; 22nd January 2013 at 07:25 PM.
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Old 22nd January 2013, 07:52 PM   #395
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XMC4500 : is this feasible?

4 x bidirectional I2S with the XMC4500 as slave connecting to a WM8580 or WM8581 codec
1 x bidirectional SPI with four chip_select
1 x I2C

I'm suggesting :

P0.0 U1C1.I2S_data_in (DX0D)
P0.1 U1C1.I2S_data_out (DOUT0) in ALT2
P0.9 U1C1.I2S_frame_sync_in (DX2A)
P0.10 U1C1.I2S_sclk_in (DX1A)

P0.4 U1C0.I2S_data_in (DX0A)
P0.5 U1C0.I2S_data_out (DOUT0) in ALT2 or HWO0
P0.6 U1C0.I2S_frame_sync_in (DX2A)
P0.11 U1C0.I2S_sclk_in (DX1A)

P1.0 U0C0.I2S_frame_sync_in (DX2A)
P1.1 U0C0.I2S_sclk_in (DX1A)
P1.4 U0C0.I2S_data_in (DX0B)
P1.5 U0C0.I2S_data_out (DOUT0) in ALT2 or HWO0

P2.2 U0C1.I2S_data_in (DX0A)
P2.3 U0C1.I2S_frame_sync_in (DX2A)
P2.4 U0C1.I2S_sclk_in DX1A)
P2.5 U0C1.I2S_data_out (DOUT0) in ALT2

P3.4 ?
P3.5 U2C1.I2C_sda (DOUT0) in ALT1
P3.6 U2C1.I2C_scl (SCLKOUT) in ALT1

P5.0 U2C0.SPI_data_out (DOUT0) in ALT1
P5.1 U2C0.SPI_data_in (DX0A)
P5.2 U2C0.SPI_sclk_out (SCLKOUT) in ALT1
P5.3 U2C0.SPI_sel0_out (SEL0) in ALT1
P5.4 U2C0.SPI_sel1_out (SEL1) in ALT1
P5.5 U2C0.SPI_sel2_out (SEL2) in ALT1
P5.6 U2C0.SPI_sel3_out (SEL3) in ALT1

Within the I2S domain, all sclk_in connecting together.
Within the I2S domain, all frame_sync_in connecting together.

All this, plus USB for updating the filters coefficients.
Configuring U0C1 as UART instead of I2S during development for updating the filters coefficients, in case USB is not working yet.

Thanks for helping.

Last edited by steph_tsf; 22nd January 2013 at 08:06 PM.
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Old 22nd January 2013, 10:08 PM   #396
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XMC4500 Relax Lite Kit-V1: is this feasible?

3 x bidirectional I2S with the XMC4500 as slave connecting to a WM8580 or WM8581 codec
1 x bidirectional SPI or I2C

I'm suggesting :

P0.0 U1C1.I2S_data_in (DX0D) @ pin 32 header X1
P0.1 U1C1.I2S_data_out (DOUT0) in ALT2 @ pin 34 header X1
P0.9 U1C1.I2S_frame_sync_in (DX2A) @ pin 33 header X1
P0.10 U1C1.I2S_sclk_in (DX1A) @ pin 35 header X1

P0.4 U1C0.I2S_data_in (DX0A) @ pin 34 header X2 (not really needed)
P0.5 U1C0.I2S_data_out (DOUT0) in ALT2 or HWO0 @ pin 31 header X2
P0.6 U1C0.I2S_frame_sync_in (DX2A) @ pin 30 header X2
P0.11 U1C0.I2S_sclk_in (DX1A) @ pin 29 header X2

P1.0 U0C0.I2S_frame_sync_in (DX2A) @ pin 21 header X2
P1.1 U0C0.I2S_sclk_in (DX1A) @ pin 20 header X2
P1.4 U0C0.I2S_data_in (DX0B) @ pin 17 header X2 (not really needed)
P1.5 U0C0.I2S_data_out (DOUT0) in ALT2 or HWO0 @ pin 16 header X2

P5.0 U2C0.SPI_data_out or U2C0.I2C_sda (DOUT0) or in ALT1 @ pin 9 header X2
P5.1 U2C0.SPI_data_in (DX0A) @ pin 8 header X2
P5.2 U2C0.SPI_sclk_out or U2C0.I2C_scl (SCLKOUT) in ALT1 @ pin 7 header X2

Within the I2S domain, all sclk_in connecting together.
Within the I2S domain, all frame_sync_in connecting together.

All this, plus USB for updating the filters coefficients.

Thanks for helping.

Last edited by steph_tsf; 22nd January 2013 at 10:12 PM.
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Old 23rd January 2013, 09:57 AM   #397
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Looks go to me, good plan for testing at least. I2S pins are grouped nicely closely together. Just build a breadboardable WM8580 board (with single row headers) first and try those combos.

Btw. This presentation claims that DAVE 3 supports among other Peripherals Specific Apps USIC (I2S, I2C, UART, SPI).

http://www.infineon.com/dgdl/DAVE-3+...35e35a63974506
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Old 23rd January 2013, 11:54 AM   #398
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Quote:
Originally Posted by mhelin View Post
Btw. This presentation claims that DAVE 3 supports among other Peripherals Specific Apps USIC (I2S, I2C, UART, SPI).

http://www.infineon.com/dgdl/DAVE-3+...35e35a63974506
Installed DAVE and downloaded the application libraries (through some Eclipse menu). The I2S application was now listed there among applications, and I was able to create a full-duplex I2S application with DMA support. Only drawback was that only 16-bit word size was supported. Got to ask Infineon why. I don't have the board so wasn't able to test. It seems CMSIS-RT OS (RTX) comes in with the build, and you have only limited support what features to disable. The generated I2S F/D DMA app used OS Semaphores at least. The generated code looks reasonable, I think you need just call some I2S002_Start() function and after that some getNextRxDMABuffer() or something, process data and store it to next Tx DMA buffers (I think) for playback.

In DAVE GUI there are also menus for manual pinning, that's nice feature.
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Old 23rd January 2013, 12:17 PM   #399
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Bad news, XMC4500 is supporting only 16-bit word length :

-------

SCTR
Shift Control Register

WLE [27:24] rwh Word Length
This bit field defines the data word length (amount of
bits that are transferred in each data word) for
reception and transmission. The data word is always
right-aligned in the data buffer at the bit positions
[WLE down to 0].
If TCSR.WLEMD = 1, the value can be updated
automatically by the data handler.
The data word contains 1 data bit located at bit
0H
position 0.
The data word contains 2 data bits located at bit
1H
positions [1:0].
...
The data word contains 15 data bits located at
EH
bit positions [14:0].
The data word contains 16 data bits located at
FH
bit positions [15:0].

Reference Manual
USIC, V2.10
17-184
V1.2, 2012-12
Subject to Agreement on the Use of Product Information

--------

Too bad they reserved only four bits for data word length register, wrong place to save bits.

Last edited by mhelin; 23rd January 2013 at 12:19 PM.
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Old 23rd January 2013, 02:19 PM   #400
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Quote:
Originally Posted by mhelin View Post
Bad news, XMC4500 is supporting only 16-bit word length

WLE [27:24] rwh Word Length

This bit field defines the data word length (amount of bits that are transferred in each data word) for reception and transmission. The data word is always right-aligned in the data buffer at the bit positions [WLE down to 0]. If TCSR.WLEMD = 1, the value can be updated automatically by the data handler.

0H The data word contains 1 data bit located at bit position 0.
1H The data word contains 2 data bits located at bit positions [1:0].
...
EH The data word contains 15 data bits located at bit positions [14:0].
FH The data word contains 16 data bits located a bit positions [15:0].

Reference Manual
USIC, V2.10
17-184
V1.2, 2012-12
Subject to Agreement on the Use of Product Information
Ok, if you listen to redbook audio mostly then 16-bit I2S data (in/out) is ok, this doesn't limit processing anyway. At least it's fine if you have analog volume controller after DAC(s). In any case your total DR will be more that that of 16-bit system because you have multiple 16-bit DACs summed in actual speakers.
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