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Old 22nd March 2012, 04:37 AM   #151
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Quote:
Originally Posted by Brunos View Post
On ARM however you can never guarantee at what cycle a particular instruction will be executed. Just an interrupt can take up to 40 cycles while the registers are dumped into memory, etc.
If you're running the whole code for every cycle, why would you need interrupts at all? Or are you wanting to update parameters based on user input in real-time. I could see there that interrupts might come in handy.

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I have worked a bit with the XMOS chips, and they do offer a great number of advantages for this type of application
I too looked at XMOS in considerable detail, and rejected it for a number of reasons for my designs. I agree technically it looks great based on performance figures. But then after I ordered an eval module I got to discover that the commercial side of their organisation isn't up to the same standards as the technical. That experience got me looking into other options and I eventually settled on ARM. After making my decision I sent feedback to XMOS and I explained to their CTO my reasons for not going with XMOS and why I see that ARM will eventually eat them. Nothing in his replies made me change my mind - indeed I received further confirmation that my decision was the correct one

Incidentally there's a recent EETimes short article here where its not clear that they have yet built up a sustainable business. They've sold half a million devices in USB it says (since inception in 2005) - and now they've introduced a dual-die part with USB PHY. I can't see the sense in that myself, for what seems such a small market. In high speed USB, there's already custom silicon which does the job better and at much lower power and its on the same die as many ARM CPUs.
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Old 23rd March 2012, 09:41 PM   #152
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Thanks for all the information, I agree that if XMOS have strange commercial practices (like their weird USB audio driver licensing) it is best to stay away. It's a pity because I find the architecture rather elegant and having a free IDE is a definite plus. Lack of fast floating point is a strong minus.
I have now read through this thread in detail, I had not realized that the XMC4500 and LPC4300 were maturing this quickly and had cheap development boards available. The cortex M4 is attractive, apart for the low clock speed. I guess the A and R versions don't have enough I2S I/O though.

It is a real pity that a DSP like SHARC does not have an open source toolchain (even just a bootloader and an ASM), as the M4 (and XMOS) are probably much slower, even at the same clock speed as I guess stuff like getting coefficients from memory, clocking samples in and out etc take at least one instruction each whereas it happens automatically on DSPs.

The guys at miniDSP seem to have done a great job, but not open source of course. I wonder where they got the spec on how to program the SigmaDSP without Sigma Studio, of if they just looked at the code that Sigma Studio generates and used that.
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Old 24th March 2012, 04:13 AM   #153
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Quote:
Originally Posted by Brunos View Post
Thanks for all the information, I agree that if XMOS have strange commercial practices (like their weird USB audio driver licensing) it is best to stay away. It's a pity because I find the architecture rather elegant and having a free IDE is a definite plus. Lack of fast floating point is a strong minus.
XMOS to me is also very elegant but I see its market niche shrinking. They're already on 65nm so not very low power (due to leakage and the high clock rate). Whereas the only M4 part on 65nm is (I think) TI's and it looks like they've hamstrung that one to just 80MHz so as not to eat into their other DSP. Which to me looks crazy coz people will just buy other people's M4 parts when they need >80MHz.

Quote:
I have now read through this thread in detail, I had not realized that the XMC4500 and LPC4300 were maturing this quickly and had cheap development boards available. The cortex M4 is attractive, apart for the low clock speed. I guess the A and R versions don't have enough I2S I/O though.
STM's dev board (I have several but not powered them up yet) is seriously cheap, presumably as a marketing exercise. But not many I2S.

Quote:
It is a real pity that a DSP like SHARC does not have an open source toolchain (even just a bootloader and an ASM),
I don't see that as a pity - to my way of thinking its more lead in ARM's pencil
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Old 24th March 2012, 01:09 PM   #154
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Another interesting technology which is coming up is the mixed ARM/FPGA processors such as Xilinx Zynq 7000, which does have an open source environment. I personally find FPGA programming quite difficult, but last year I have tried (for work) the Actel smartfusion, which is a cortex M3+FPGA. You program it just like any other ARM, say with Keil, but with the possibility of adding custom ports/DSP instructions etc. The design tool then generates the c drivers automatically, and you just call the functions from your ARM code.
For an open platform and FPGA does offer some advantages, and they have really come down in prices in the last few years (the Actel dev board was 90$).
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Old 12th April 2012, 03:25 AM   #155
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Default Another example of using LTSpice in FIR filter design

OK, now getting back to the original purpose of this thread, which was to encourage people to try out LTSpice as a digital filter design tool and hence establish a base of 'open source' digital filter designs.

Here's a design flow I've played around with this week as a rather different way to design digital FIR filters than the traditional MATLAB and equiripple style approach. As Julian Dunn pointed out in a paper, there are some hidden pitfalls of using equiripple filters in digital audio. Bruno Putzeys has picked up on his paper too. In a word - time smearing.

So in an attempt to avoid time smearing I decided to explore how using an analog filter as a template for a digital one might work out. Here's a 4th order MFB lowpass that I'd like to have as a digital filter. Its the LP half of what I've been using (LR4) in my active speakers of late. But here you'll notice there's a delay line for the HP rather than the traditional two opamp Sallen-Key - the idea here is that with digital filters we can use delay elements for free (unlike with analog filters) so why not build a subtractive cross-over? Doug Self points out in his recent book on active XOs that subtractive XOs have the weakness in analog implementations that they depend on matching for their stop-band performance. Well in digital, matching doesn't need to be an issue.

LTSpice allows us to set up both frequency response and time domain characterisations - I've done that here. First check the frequency domain performance is what we expect. Then do a time domain analysis with a single cycle impulse - given that this is to work at 44k1, a pulse 22.7uS wide is chosen. By trial and error I fiddled the group delay (integrator time constants) to match an integer number of samples (6 in this case) - the precise crossover point isn't as important as getting the right delay.

With the delay line matching the filter's asymptotic group delay, the HP subtracted output looks like the last plot.
Attached Images
File Type: png MFB_4th_sch.png (10.9 KB, 230 views)
File Type: png MFB_4th_freqresp.png (5.6 KB, 219 views)
File Type: png impulse_MFB.png (3.9 KB, 219 views)
File Type: png 4th_MFB_HP.png (5.9 KB, 218 views)
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Old 12th April 2012, 03:56 AM   #156
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Default Turning an analog filter into a digital one

The next step is one I'd like eventually to automate - I'm sure its not hard to do that, but I did this manually to get a feel for what goes on. I tabulated the impulse response plot, having normalized it (by trial and error) to get 1LSB = 1mV. I decided to go for 12bit coefficients, which means 2.047V is the maximum representable amplitude. To do this, just scale the amplitude of the impulse to get the peak close to the maximum digital value. I needed 11.8V to achieve 2.031V as a peak value (the waveform goes slightly beyond this between samples).

The values of the impulse function I wrote down at intervals of the sample rate (22.6uS approx). These values then become the coefficients for the FIR filter which we build using delay elements.

The pic is a little cramped owing to not having too much resolution on my screen, but down the left are the coefficients expressed as a column of .param's - the summation is done with the series voltage sources over at the right.
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File Type: png FIR-delay-sch.png (22.6 KB, 216 views)
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Old 12th April 2012, 04:08 AM   #157
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Default Here's what the synthesized FIR looks like in the frequency domain

The stop band has wiggles - these are the result of both quantizing the coefficients to 12bits and truncating the impulse response in time to a relatively small number of samples (31 in this case). I've not used any windowing function to smooth off the discontinuities just tweaked the final few coeffs by hand to see how the stop band wiggle shifts around.
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Old 12th April 2012, 04:39 AM   #158
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I haven't gotten around to building a digital XO in this way yet but I hope to do so sometime this year The computational complexity is low in going for such an arrangement - the FIR has 31 taps meaning fewer than 3MMACs for a stereo one. The highpass is just a subtraction, so not exactly taxing An LPC1113 will be able to manage this mathematical burden very comfortably - indeed it probably would be able to be underclocked which would mean the power demands are going to be single digit mA (at 1.8V) - doing it with 5532s would take 4 chips and 320mW.
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Old 12th April 2012, 05:31 AM   #159
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If you want an LR4 cross why not use IIR biquads?
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Old 12th April 2012, 05:35 AM   #160
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Call it my rebellious streak. I can understand better what's going on with FIRs, and don't have any kind of intuitive handle on how IIRs work or what their shortcomings might be (limit cycles, potential truncation effects). Until I find I'm out of computational power I prefer to stick to FIRs
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