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Old 6th February 2012, 11:02 AM   #131
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All those look expensive and not very good sounding. My imagined semiconductors BOM looks like this :

WM8805 9元
LPC1113 9元
TDA1387 * 4 2元
AD605 * 2 6元
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Old 13th February 2012, 08:20 AM   #132
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That's my idea of DSP platform in single picture

Call it MRD /market requirements document/.
Next stage would be SRS /system requirements specification/ and then HDS /hardware design specification/.
After the HDS - right into boards layout.

Clocking and PSU schemes should be drawn, as i want to try both slave and master for the modules.

Also, as i look at it... There is not enough space for everything, if i go with my standart "5x5cm" board sizes for modules + 10x10cm for mobo.
In addition, some modules should have ability for daisy-chaining - waste of board space and major ground cutouts. They should carry i2s lines too...
Some of them should be able to inject into i2s bus (ASRC for example)...

Moreover, 5x5cm board is fine for my tas3108, but could be too small for other DSPs.

PSU board is just 5x5cm, therefore no largish caps is possible = external PSU with rectifiers and large caps should be used. PSU board will contain just the regs + surrounding circuit. Maybe sticking to fixed regs will save some space, and won't affect much the performance, as every board should take care of it's own supply filtering.

Some MCU would help too, for the configuration over i2c, although i don't want to add another degree of complexity.

Looks overkill... 9 daughter boards to start from
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Old 13th February 2012, 09:04 AM   #133
chaparK is offline chaparK  Luxembourg
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Hi s3tup!

Could you throw a bit of text to explain your graph?
Looks good but i can't interpret the various columns.

Best

Nick

Quote:
Originally Posted by s3tup View Post
That's my idea of DSP platform in single picture

Call it MRD /market requirements document/.
Next stage would be SRS /system requirements specification/ and then HDS /hardware design specification/.
After the HDS - right into boards layout.

Clocking and PSU schemes should be drawn, as i want to try both slave and master for the modules.

Also, as i look at it... There is not enough space for everything, if i go with my standart "5x5cm" board sizes for modules + 10x10cm for mobo.
In addition, some modules should have ability for daisy-chaining - waste of board space and major ground cutouts. They should carry i2s lines too...
Some of them should be able to inject into i2s bus (ASRC for example)...

Moreover, 5x5cm board is fine for my tas3108, but could be too small for other DSPs.

PSU board is just 5x5cm, therefore no largish caps is possible = external PSU with rectifiers and large caps should be used. PSU board will contain just the regs + surrounding circuit. Maybe sticking to fixed regs will save some space, and won't affect much the performance, as every board should take care of it's own supply filtering.

Some MCU would help too, for the configuration over i2c, although i don't want to add another degree of complexity.

Looks overkill... 9 daughter boards to start from
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Old 13th February 2012, 10:05 AM   #134
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Each block color represent's it's pin compatability group.

"DSP motherboard" and "Stand-alone DACs" represent physical layouts of blocks in the devices.
"Stand-alone DACs" have 2 columns - with and without ASRC module.

"Input module options" lists possible input modules, which will be interexchangeable (pin compatable).

The last column - is optional 8-ch RS485 receiver board for replacing the DSP board with PC-sourced i2s bus taken from Envy24 cards. This board should be pin-compatable with DSP board, because it should give 4 i2s lines on it's output.
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Old 16th February 2012, 05:01 AM   #135
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Default Freescale Kinetis K10

Potentially the lowest cost M4's to date, but only 50MHz :

http://cache.freescale.com/files/32b...=Documentation
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Old 16th February 2012, 07:59 AM   #136
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Unfortunately those 48-pin Freescale K10 chips only provide one I2S. You thus need at least two K10 chips for a 2-way crossover. On top of this, as developer, you need the JTAG/SWD Segger J-Link Debug Probe at 300 dollars or the JTAG/SWD Red Probe+ at 150 dollars talking to a solid Integrated Development Environment having a correct Freescale K10 installed base and support.

On the other hand the Microchip 28-pin PIC32MX1 or PIC32MX2 provides two I2S enabling a one-chip 2-way crossover. As developer, you need the Microchip ICD3 Debug Probe at 200 dollars and the Microchip MPLABX Integrated Development Environment.

Today, what's still missing in the ARM Cortex-M4 armada, is a two or three dollar chip featuring four I2S ports. Would be nice, isn't ? Today, a chip like the STM32 F4 costing 10 dollars in small quantities, only provides two I2S. It remains to be proven that the JTAG/SWD Red Probe+ can hook on it.

But wait a minute, there will be the T.I. AM3358 (an ARM Cortex-A8) costing 10 dollars in small quantities, equipped with eight I2S pins, enabling a one-chip 4-way crossover. Total cost is actually more, as you need external Flash and RAM. A credit-card sized 4-way xover is possible using four chips : the AM3358 C, the Flash, the RAM, and a 7.1 Audio Codec like a WM8581 or CS42526.
Nearly available today is the 89 dollars "BeagleBone", a credit-card sized board hosting the AM3358 C, the Flash and the RAM.
The Open Source DSP XO could thus materialize into a "Digital Audio Cape" for BeagleBoard, hosting a WM8581 or CS42526 Audio Codec, plus maybe a DIR9001 chip (ASRC), target price 50 dollars or so.
Another good news is the existence of Tin Can Tools Flyswatter USB to JTAG in-circuit debugger and programmer designed for ARM Cortex-A8 cores, at 50 dollars. The corresponding Integrated Development Environment is OpenOCD.
Within OpenOCD, as this is an open system, one can introduce high level Digital Audio features easing the do-it-yourself approach.
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Old 16th February 2012, 08:16 AM   #137
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Quote:
Originally Posted by steph_tsf View Post
Unfortunately those 48-pin Freescale K10 chips only provide one I2S. You thus need at least two K10 chips for a 2-way crossover.
Yes, that's true - though as the 10k+ price shown by Freescale is under $2, its hardly going to break the bank is it? At 50MHz they'll do 62.5MIPs tops, so a single one is probably a bit underpowered anyway.

Quote:
On top of this, as developer, you need the JTAG/SWD Segger J-Link Debug Probe at 300 dollars or the JTAG/SWD Red Probe+ at 150 dollars talking to a solid Integrated Development Environment having a correct Freescale K10 installed base and support.
No need to spend so much - check out the link I've given above to an eBay option.

Quote:
On the other hand the Microchip 28-pin PIC32MX1 or PIC32MX2 provides two I2S enabling a one-chip 2-way crossover. As developer, you need the Microchip ICD3 Debug Probe at 200 dollars and the Microchip MPLABX Integrated Development Environment.
The downside of that is that its an investment in Microchip - whereas buying an ARM debugger/IDE gives the choice of multiple silicon vendors. Microchip being a single company can't compete with the choice of clock speeds, peripheral variety, RAM/ROM options, pin-outs and packages that comes from having an ecosystem at one's disposal.

Quote:
Today, what's still missing in the ARM Cortex-M4 armada, is a two or three dollar chip featuring four I2S ports. Would be nice, isn't ?
We can but dream eh? But I think paralleling chips is a fine solution at the current cost (and power requirements) of these parts. Its also a much more expandable route to dedicate a CPU to each driver (or perhaps each stereo pair). Then if you want to add in a sub at a later date, just get another CPU+DAC combination.
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Old 16th February 2012, 11:04 PM   #138
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Quote:
Originally Posted by abraxalito View Post
I think paralleling chips is a fine solution at the current cost (and power requirements) of these parts. Its also a much more expandable route to dedicate a CPU to each driver (or perhaps each stereo pair). Then if you want to add in a sub at a later date, just get another CPU+DAC combination.
Nice modularity and expandability, indeed. So if you put a room equalizer as front-end, a N-way stereo crossover would require N+1 Freescale K10 chips. As developer, how would you program and debug this ? SWD multidrop instead of JTAG ? Is it available now ?
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Old 16th February 2012, 11:20 PM   #139
chaparK is offline chaparK  Luxembourg
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I'm not sure that DSP for loudspeaker is such a complicated thing that you need debugging access across the whole system.
You can debug 1 chip, then you expect the other ones to be nearly identical.
If you want to make it the hard way, you can unit test each routine, then system test the whole thing with real life inputs.

But yeah - the effort/cost is probably not worth given that you have single chips around that will do the same job as 10 cascaded 50MHz chips...

Quote:
Originally Posted by steph_tsf View Post
Nice modularity and expandability, indeed. So if you put a room equalizer as front-end, a N-way stereo crossover would require N+1 Freescale K10 chips. As developer, how would you program and debug this ? SWD multidrop instead of JTAG ? Is it available now ?
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Old 17th February 2012, 01:05 AM   #140
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Quote:
Originally Posted by steph_tsf View Post
Nice modularity and expandability, indeed. So if you put a room equalizer as front-end, a N-way stereo crossover would require N+1 Freescale K10 chips. As developer, how would you program and debug this ? SWD multidrop instead of JTAG ? Is it available now ?
As far as I'm aware, yes. When I fire up my J-Link it tells me its using SWD (if my memory serves). But I haven't tried this with multiple CPUs on the same wire. So that's an experiment for the future.

I wouldn't debug this with all chips running myself though, I'd do this in two stages. Debug the code in just one CPU and get that working first. Then hopefully the only differences between different CPUs would be coefficients, not code.
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