Open Source DSP XOs

[sgpu]

Hi,

Thought I would chime in on here. I'm developing a board using the DM8148. It has a 1Ghz A8 and a 750MHz C674x DSP. I've also maximized the pin mux settings to allow a possible 26 pair pairs of i2s I/O.

More can be found here
DaVinci Digital Video Processor - TMS320DM814x SOC - TMS320DM8148 - TI.com

My genius coder is at work on the Mistral EVM to allow 10 simultaneous pairs of i2s or DIT output on McASP0 at 24-bit 96KHz.

By the sounds of things you can port your work to the DM8148.

Here's the initial hardware spec sheet.

http://www.lucidchart.com/publicSegm...e-5f7d0a48117a

[rsdio]

Originally Posted by sgpu

I'm developing a board using the DM8148. It has a 1Ghz A8 and a 750MHz C674x DSP. I've also maximized the pin mux settings to allow a possible 26 pair pairs of i2s I/O.

My genius coder is at work on the Mistral EVM to allow 10 simultaneous pairs of i2s or DIT output on McASP0 at 24-bit 96KHz.

Very promising. I am a big fan of the TMS320 family and have significant experience programming these DSP chips in C and assembly.

Question: Why did you only use 5 of the McASP peripherals and not all 6? Were those particular pins needed for other critical functions?

When you spec 26 pairs, that implies that you have connected McASP5, McASP4, McASP3, McASP2 and McASP0. What about McASP1? It is the only other McASP peripheral which can accept an independent receive clock (bit and word frame). The remaining McASP peripherals only have output clocks, and are thus seemingly no good for receiving data that is externally clocked. For example, it might be nice to have HDMI audio input on McASP1 and AES3/SPDIF input on McASP0, although I admit that those are clock-compromised standards.


When you say 10 simultaneous pairs, I assume that you mean 10 simultaneous stereo streams. McASP0 only has 10 pins that can operate as data receive or data transmit, but not both at the same time. However, I get the impression that the system could handle 10 simultaneous multichannel-surround streams, provided they all used the same format. EDIT: When I say multichannel-surround, I am thinking not only of, e.g., 7.1 full-range surround but also multi-way crossover outputs for a single speaker cabinet with multiple drivers.

[abraxalito]

Originally Posted by sgpu

By the sounds of things you can port your work to the DM8148.

I reckon people could, but I'd not recommend it. Your project has rather different philosophy to mine. If you recall, you said:

Originally Posted by sgpu

RF is our nightmare but somewhere along the line you have to compromise on noise.

My idea is not to compromise on noise and hence use only enough MIPs to get the job done.

[sgpu]

We have
McASP0 - 10 data pins
McASP1-4 - 4 data pins each.

Each McASP has two time domains. So you can xm and rx at whatever you like simulaneously but the format must remain the same. Ie, xm 24/96 i2s, rx 16/44.1 i2s. We have 5 pins xmit and 5pin rx on McAS0. Also, each pin can xm/rx TDM to supported ADC/DAC chips...

McAsp 5 not used as pin muxed with mcasp4.

[Trevor White]

Originally Posted by sgpu

Hi,

Thought I would chime in on here. I'm developing a board using the DM8148. It has a 1Ghz A8 and a 750MHz C674x DSP. I've also maximized the pin mux settings to allow a possible 26 pair pairs of i2s I/O.

More can be found here
DaVinci Digital Video Processor - TMS320DM814x SOC - TMS320DM8148 - TI.com

My genius coder is at work on the Mistral EVM to allow 10 simultaneous pairs of i2s or DIT output on McASP0 at 24-bit 96KHz.

By the sounds of things you can port your work to the DM8148.

Here's the initial hardware spec sheet.

http://www.lucidchart.com/publicSegm...e-5f7d0a48117a

Isn't that a fine pitch BGA part ?? Who's going to solder that on for you ?

[sgpu]

Soldering? A favor from a local assembly firm, I know the directors. :-)

Lifted from 16.1 of the TRM ( http://www.ti.com/lit/ug/sprugz8/sprugz8.pdf )
"The McASP consists of transmit and receive sections that may operate synchronized, or completely independently with separate master clocks, bit clocks, and frame syncs, and using different transmit modes with different bit-stream formats. The McASP module also includes serializers that can be individually enabled to either transmit or receive."

[sgpu]

Originally Posted by rsdio

Question: Why did you only use 5 of the McASP peripherals and not all 6? Were those particular pins needed for other critical functions?

The pin mux utility is very useful here. We could increase McASP1 to 8 data pins but we would lose 2 data pins off McASP3,4 as a result.

Question: Why did you only use 5 of the McASP peripherals and not all 6? Were those particular pins needed for other critical functions?

The remaining McASP peripherals only have output clocks, and are thus seemingly no good for receiving data that is externally clocked.

Pin muxing makes it quite difficult to have all McASP units active. I made the decision to keep a few quads for 8ch i2s per McASP. McASP3,4,5 were intended to be outputs. I will be adding external CLKin options for each of these too if an external board has its own master clock that the McASP can slave from.

McASP0 only has 10 pins that can operate as data receive or data transmit, but not both at the same time.

Not true. Saying that, there is not a great deal of support in the recent PSP for any of what I'm planning. I have a developer extending the EVM McASP and ALSA driver. Initially, each McASP module will be presented to linux as independent sound cards for testing. The pin muxing, for now, will be set with the boot loader. I need advice whether or not this can be changed on the fly through registers.

I am deciding what to do about a master onboard clock. I can install install several low noise master clocks if needed. Using registers, each McASP time domain can be set to use clocks from the internal PLL, or XO. The clock structure on the DM8148 needs some serious thought.

[Trevor White]

Originally Posted by sgpu

Soldering? A favor from a local assembly firm, I know the directors. :-)

Lifted from 16.1 of the TRM ( http://www.ti.com/lit/ug/sprugz8/sprugz8.pdf )
"The McASP consists of transmit and receive sections that may operate synchronized, or completely independently with separate master clocks, bit clocks, and frame syncs, and using different transmit modes with different bit-stream formats. The McASP module also includes serializers that can be individually enabled to either transmit or receive."

what development system do you use to write code for this device ??

[sgpu]

Originally Posted by Trevor White

what development system do you use to write code for this device ??

Whatever floats your boat for linux development. The board will run a wide variety of OS. I am currently booting Ubuntu or Gingerbread on the EVM. Have you come across the BeagleBoard before? I'm building a more powerful version of that.

[sgpu]

I don't want to hijack this thread. I started another here ARM/DSP based open source Hi-Fi

Clock wise my initial plan was to have three good low noise clocks.
- AUXOSC is routed to most of the A/V subsystems including HDMI by way of an internal PLL.
- XREF are external fixed clocks. Developers will be able to chose which clock source to use for their McASP xm/rx domain. Either the internal PLL from AUXOSC or between two low noise ref clocks for 44.1/48 sampling rates.

I will be running some tests in a few weeks by backfeeding McASP0 outputs to McASP1 inputs to check the PCM streams bit for bit. I will also be testing using the clock sources on the EVM. You can buy these for $2000 from TI. Info and schematics here. http://www.mistralsolutions.com/pes-...dxevm8148.html The EVM uses a http://search.digikey.com/us/en/prod...45-1-ND/482133 to distribute clocks to the AIC32 and XREF.