Sorry if this is was already touched upon, I haven't found a clear answer using the search function. Is it recommended that a buffer be used in conjunction with these circuits? Leach's article seems to suggest that he's taking the output directly, but multiple users seem to be following the cen/sen with the jg buffer.
Sorry to continue insisting, perhaps you did not see my questions so here i go again. I'd really like any answer you could give me regarding the questions I have done to you.
First. Regarding the possibility that r1 and r2 may be changed from 560k to 200r to get a stable output with an offset in the input current (PCM1792). I know u are testing a solutions to this kind of DACs, but probably means the addition of a CCS. It is not my intention that you do special tests to get an answer, i only want to know if there is an error or basic theoretical impossibility to do it, and then decide whether it’s worth doing. Perhaps some value or other component that had to be modified, or increase the total number of Idss of each channel, or some other aspect.
Second. Is it possible to determine the offset voltage due to a mismatch of JFETs, keeping the circuit disconnected from a DAC? Perhaps connecting the input to ground?
Thanks.
Cheers.
First. Regarding the possibility that r1 and r2 may be changed from 560k to 200r to get a stable output with an offset in the input current (PCM1792). I know u are testing a solutions to this kind of DACs, but probably means the addition of a CCS. It is not my intention that you do special tests to get an answer, i only want to know if there is an error or basic theoretical impossibility to do it, and then decide whether it’s worth doing. Perhaps some value or other component that had to be modified, or increase the total number of Idss of each channel, or some other aspect.
Second. Is it possible to determine the offset voltage due to a mismatch of JFETs, keeping the circuit disconnected from a DAC? Perhaps connecting the input to ground?
Thanks.
Cheers.
a) There has been solutions by other people published here with the PCM1794, proven to work.
b) We have published a rough outline of our solution, and we shall publish the full solution when we are ready.
In our solution we did not have to change the two resistors to 200R.
c) The function of R1 and R2 has been explained in the article, which you can download for free.
d) If you wish to experiment with variants of the circuit according to your interpretation, you are most welcome.
e) You can always test any variations of the basic circuit in LT Spice (freeware) before building.
Patrick
b) We have published a rough outline of our solution, and we shall publish the full solution when we are ready.
In our solution we did not have to change the two resistors to 200R.
c) The function of R1 and R2 has been explained in the article, which you can download for free.
d) If you wish to experiment with variants of the circuit according to your interpretation, you are most welcome.
e) You can always test any variations of the basic circuit in LT Spice (freeware) before building.
Patrick
All of them mean the addition of CCS plus the corresponding PS for these, Servos as well.
Thanks for that, but I’m afraid that it will be a CCS. Don’t get me wrong, I’m not saying that CCS is bad; it’s just a personal preference that I don’t like CCS as the answer in this particular circuit.
200R addition means no CCS, if it works, but the circuit consumption rise and the wattage of the resistor rise as well. Probably additional JFETs need to be added to increase the total Idss and handle the offset.
I already read the article, and the explanation about the r1 and r2 is just a potential divider to set the floating power supply symmetrically about input ground DURING START UP. But in the simulation that I load up in the post #1616, when lowering this resistors, the output signal gets 5.6 Vp-p (7.8 mA x 725R), and an offset of 4.5 V (6.2 mA x 725R). Overall, the output signal became consistent with the currents on the input (7.8 mA p-p, 6.2 mA DC), in other words, r1 and r2 work additionally during the normal operation. All of this off course, on the simulation.
Thanks, I was just seeking for basic errors that my proposal could have, nothing more.
As I mentioning, I am already testing this ideas on SIM.
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What's the disadvantage with this configuration instead of batteries? Running a dual regulated supply and just floating the ground. Do you get drifting dc voltage on the output?
link for the buffer
Hi Patrick
please let me send a link for interesting buffer with floating ps with similar topology for CEN: http://www.diyaudio.com/forums/pass...e-follower-configurations-44.html#post3834549
Hi Patrick
please let me send a link for interesting buffer with floating ps with similar topology for CEN: http://www.diyaudio.com/forums/pass...e-follower-configurations-44.html#post3834549
I didn't make a dual regulated supply, but two completely isolated PS, starting by using separated transformers for each. Of these, the positive and negative terminals of each regulated PS, was connected as suggested in the schematic. I do not use the term "ground" or reference for the negative terminal on both supplies, because these sources are floating.
Regarding noise, only by ear, I fail to perceive any of it at full Iout of the Dac (7.8 mA pk-pk). I only get some noise when using digital volume, which means lowering Dac pk-pk Iout and, increasing with it, the noise in proportion to the signal.
Evaluation Kits and parts
8x matched 2sk170BL's from reliable FetAudio.com (7.6ma)
4x WIMA 0.1uF Polypropylene Film Capacitors
2x WIMA 330pf Pulse Film Capacitors
4x Nichicon MUSE BP 220uF 16v
4x PRP 560k 1% resistors
I also have some parts:
8x matched 2sk170BL's from reliable FetAudio.com (7.6ma)
4x WIMA 0.1uF Polypropylene Film Capacitors
2x WIMA 330pf Pulse Film Capacitors
4x Nichicon MUSE BP 220uF 16v
4x PRP 560k 1% resistors