Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

S/PDIF receiver jitter measurement report: WM8805 vs. FIFO

Maybe I don't have to post the jitter measurement result or try to prove something here, because the principle is clearly over there, everybody knows. On the other hand, I'm not a certificated testing lab, I feel a bit unfair testing on a third party product and get it compared with my own project. But being as a R&D engineer, I think telling the truth is more important than just talking a theory.

Since somebody is interested in the real jitter measurement results on popular S/PDIF receivers, such as WM8805 (fortunately, I still keep my WM8741 DAC with WM8805 DIR), as well as the MCLK output of my FIFO, it seems I need doing some real testing:).

Testing conditions

Equipment: LeCroy real time digital oscilloscope
Bandwidth: 1GHz
Sample rate: 8GS/s (25GS/s max)
Probe: 50 ohm coaxial, 12 inch
Sample size: 10,000
Jitter noise floor: 2ps
Jitter testing software: Jitter measurement package JTA
Jitter measurement: period jitter
S/PDIF source: Krell KPS 20i/L CD transport 44.1KHz
S/PDIF connection: 3 feet 75 ohm coaxial cable

Test1: WM8805 output MCLK jitter

Testing setup:

Jitter display: 50ps/DIV
see the first picture for details

Testing result:

Period jitter RMS:37.02 ps
Period jitter peak-to-peak:+-150ps
Jitter distribution: Gaussian
frequency: 11.2891MHz

Please see the second screen shot picture for details

Test2: MCLK jitter after FIFO

Testing setup:

Feeding WM8805 I2S output into FIFO, and then measure the output MCLK of the asynchronized I2S stream.
Oscillators on the dual xo clock board: onboard generic 11.2896MHz XO
FIFO running at *256Fs
Jitter display: 10ps/DIV
Please see the third picture for details

Testing result:

Period jitter RMS:5.13 ps
Period jitter peak-to-peak:+-18ps
Jitter distribution: Gaussian
frequency: 11.2897MHz

Please see the fourth screen shot picture for details

Some comment:

1. Please note, the jitter noise floor of my scope is 2ps, so the actual jitter numbers should be even smaller. Since it’s Gaussian jitter, we can roughly estimate the actual jitter from the RMS result. However to get more accuracy jitter testing result, or to test a really nice clock, we need better tools, I like LeCroy new 65GS/s scope, as well as Agilent E5052B phase noise analyzer, but I couldn’t afford those house price toys. However I don’t think we need them to get today’s testing conclusion, by comparing with the two testing result, it’s already telling the story.

2. Actually, my testing result on WM8805 is very close to the specification which was 50ps RMS. My result is even better, I think it was because I have a better S/PDIF source. However, the peak-to-peak jitter was poor, I don’t believe WM8805 can make any good DAC without help of other technology. Sorry about telling the truth, I know there are a lot of Wolfson users. Qusp is a talent, he predict the result a couple of days ago:). Yes, it “20x” better, of cause for CCHD957 or equivalent low jitter XO, at least.

3. Again, I’m neither from a certificated test lab, nor a testing engineer. Both my measurement setup and my equipment could be wrong. So, my testing result is just for reference. It doesn’t prove anything.

Conclusions:

I will leave this part to other members:).

Ian
 

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haha! what can I say, i'm jitter clairvoyant ;) simply by laying my hands on the fifo it tells me the result. alternatively you may think me an insane person... you choose

go go generic clock! so its really superb to see that our faith in good theory with proper application works as expected. if you do ~'everything' right, the numbers follow suit.
I think the above will shut some doubters up and give the rest of us who have shown faith from the beginning, a justifiably smug glow lol. even with the $2? demo XO it pwns the competition and from a spdif input no less! I can only imagine the illusive results that would come from NDK.

Kudos Ian! Kudos! I love how you had to cripple the unit to make it measurable HA!

this result is really something for you to be proud of Sir! a singular man in his house, with 'limited' resources.

Incredible
 
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Hi Ian,

Why are you putting .1uF ceramic capacitor between an unconnected (pin4) pin of ADP151 and ground?

Kind regards,
Mihai

you need to be more specific, quoting a random new years greeting made by someone else is not giving very good context for your question. for example the LFCSP package of the ADP151 has pin 4 as the enable pin.

but i'm not sure which ADP151 you are referring to. also I believe Ian allowed for the alternative use of TPS series regs on some boards
 
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Maybe I don't have to post the jitter measurement result or try to prove something here, because the principle is clearly over there, everybody knows. On the other hand, I'm not a certificated testing lab, I feel a bit unfair testing on a third party product and get it compared with my own project. But being as a R&D engineer, I think telling the truth is more important than just talking a theory.

...

Ian, very nice Results!

Do you think you can do better than 5 ps RMS? Isn't the jitter dominated by the flip flop?
 
hes already done better than 5ps RMS, its 5ps RMS including the 2ps noise floor of his measurement rig and this is with only the generic test XO in place, not the crystek or si570.

As he said, he knew given the results and his measurement capability that measuring with the crystek would result in a number dominated by his noise floor, so he intentionally crippled the fifo to get a somewhat more meaningful result

so rather than the flipflop dominating, here its the noise floor and the generic XO that dominates the results, it would seem the fifo and buffer/flipflop itself has jitter hardly worth mentioning.
 
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Thanks for taking the measurements, I understand that technically they are relative without NIST traceablity etc. But your numbers fall in line with the best commercial usb converters out there (Pat's stuff). But this fifo has two big advantages for DIY geeks.

#1 I2S output
#2 higher clock rates, especially 188.4 & 352.8khz

It is really incredible how good these mearements were with only a 1ghz scope and a generic scope.

We all know that jitter is more troublesome on both ends the faster we go, its exponential, its why the ESS is so troublesome and part of the reason why people like NOS, etc.

So I think its important to ask if the performance is as good with a faster clock, ie where does it come unglued 25.597 ... 90+ MHZ ? Or way higher by inductive reasoning ?
 
I've never seen jitter specs for flip flops, just people saying figures here and there with figures higher than jitter values of clocks.

nope I think in this case with the high quality parts Ian is using they are contributing less than the 0.5ps of the ccdh975, not sure of the exactly amount but we theorised that the jitter of the fifo would still be less than 1ps with both the clock jitter and flip flop. not RMS
 
Thanks for taking the measurements, I understand that technically they are relative without NIST traceablity etc. But your numbers fall in line with the best commercial usb converters out there (Pat's stuff). But this fifo has two big advantages for DIY geeks.

#1 I2S output
#2 higher clock rates, especially 188.4 & 352.8khz

It is really incredible how good these mearements were with only a 1ghz scope and a generic scope.

We all know that jitter is more troublesome on both ends the faster we go, its exponential, its why the ESS is so troublesome and part of the reason why people like NOS, etc.

So I think its important to ask if the performance is as good with a faster clock, ie where does it come unglued 25.597 ... 90+ MHZ ? Or way higher by inductive reasoning ?

the ESS itself works better with higher speed clocks and Ian seems to be confirming that the fifo is working better with higher speed clocks. remember there is no mechanism here in the fifo after the clocks to be producing higher noise at higher speeds, effectively we are getting the datasheet jitter specification for the higher speed clock, plus the nominal flip flop jitter, the flip flops are designed to work at MUCH higher speeds than what we are talking about here, so they may even perform better as the speed increases.

also.. troublesome? I dont find the ESS troublesome for reasons of higher speed, it likes the higher speed, puts more demands on the power supply but thats pretty under control by decent designers, as the speeds are really not that high in the greater scheme of things, just high for audio so needs different treatment

why ESS is troublesome for some used to other dacs is, to meet its analogue specifications is a tall order for the analogue stage and power supply, plus its a pretty delicate low impedance current source, but has higher current output than most so rules many small signal low noise devices out.
 
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At this performance level the options for measuring jitter are limited. You can spend a bundle on one of the fancy measuring systems and that makes sense if you need to measure a variety of different sources. However for specific sources you can get very good results using a reference oscillator and a double balanced mixer. If you need to go well below the noise of your reference oscillator there are techniques using two reference oscillators and correlation to extract the phase noise that is common. More here: Techniques for Measuring Phase Noise . Phase noise above the sample rate won't affect the output because its conversion is above the system bandpass. This makes it harder to convert from the cycle to cycle measurements (with an effective bandwidth of 1/2 the sample rate I think) to the final audio output.

You can get a Wavecrest with a 2 pS noise floor, and for less that $700. But it still won't tell you what you want to know as well as either the above method or looking at the output of the dac, which is what matters. Looking at the raw clock is a good analytic tool for seeing how much it has been degraded. The phase noise measurements are the best way to make the measurements.

Main Page has added the ability to make the cross correlation measurement using a sound card. You still need two reference oscillators and double balanced mixers. You can get a noise floor of -170 dBC with care. The minicircuits mixers are certainly good enough to start with. The Crystek oscillators may be good enough but you really need a voltage control input to phase lock the oscillators.
 
Hi Ian!
First you measures period jitter not phase, correct you post.
To measure with better accuracy and lower minimum jitter values with you lecroy osc (because of not perfect timing for interliving adc, amplitude-time distirtion conversion etc.) you need to
1. Apply ERES (3bit) function
2. Apply SinX interpolation before eres function if you sampling rate is lower than 4Gs
3. You signal must have maximim amplitude, just before clipping of ADC, use variable attenuator of you scope to maximize signal level.
4. Rise time of you signal should be 3-4ns for lowest osc jitter

regards, Nazar
 
you need to be more specific, quoting a random new years greeting made by someone else is not giving very good context for your question. for example the LFCSP package of the ADP151 has pin 4 as the enable pin.

but i'm not sure which ADP151 you are referring to. also I believe Ian allowed for the alternative use of TPS series regs on some boards

My mistake ... the quote didn't take the schematics also. This is the post, and pin4 is NC for that type of package.

http://www.diyaudio.com/forums/digi...imate-weapon-fight-jitter-36.html#post3302605