Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

slartibartfasst · 2012-11-21 10:30 pm

Thanks, Qusp. That is good news.

hochopeper · 2012-11-22 2:59 pm

hochopeper said:
Thanks for the protocol definition Ian, I will start my own DAC controller design shortly and this info will be invaluable. I want my controller to be network accessible so I've decided to start fresh with mine. For additional integration, I might end up using my network facing controller as the playback device and integrate the playback software with the control software. More details will become evident as I start working on it I'll hopefully get started on that in the next week or two, in readiness for GBIII

One issue that has only just dawned on me is that in the Dual XO manual you refer to J12 on the FIFO board being available to be used for mute signal. You really have thought of everything already! Is anyone using this already? I haven't seen anyone asking or discussing it. However, the FIFO manual that I have saved here doesn't describe the behaviour of this output port. Maybe I'm looking at the wrong manual? What is the behaviour of this pin? Is it active high or active low, does it need an external pull up? Can this be run through isolator if i2c is not used to the dac? I was going to implement a similar mute function in my controller but if you've already done the hard work, this really might be better implemented by the FIFO directly for lower latency.

Chris

I wrote the first code for the ARM v7 + linux/python DAC/si570 controller tonight. Only ~40 lines so far, this should be fun! As a result, Ian, I wanted to cofirm something since I haven't worked with serial a great deal previously. In your protocol are you actually sending the commas? Or are you just using them to denote the separation of each hex character?

Regardless here's what I had in mind as for the custom freq definition part of the code:

Code:

#user configurable lookup, dict indices per fs ie freqmap[3] will return the index of xofreq that corresponds to desired mclk
#default to 45/49MHz mclk for my ES9023
freqmap =  {0: 4, 1: 5, 2: 4, 3: 5, 4: 5, 5: 4, 6: 4, 7: 5, 8: 4, 9: 5}

fs = {0: '22kHz' 1: '24kHz', 2: '44.1kHz', 3: '48kHz', 4: '88kHz', 5: '96kHz', 6: '174kHz', 7: '192kHz', 8: '352kHz', 9: '384kHz'}

xofreq = {0: '11.2896MHz' 1: '12.2880MHz', 2: '22.5792MHz', 3: '24.5760MHz', 4: '45.1584MHz', 5: '49.1520MHz', 6: '90.3168MHz', 7: '98.3040MHz'}

def customfreq(data):
  string = '0xA5,OxC8,' + freqmap[data] + ',0x5A'
  Serial2.write(string)

NB, python code so syntax is different to C, those are comments following the '#'

Simple to use the data included with the 0xC1 command to index a frequency mapping dict that will store mclk for each fs. Code above doesn't need critique or feedback, just showing as a snapshot of what I had in mind for that part, it'll change I am sure before long.

I might start on a Web UI soon, I have time on my side with GBIII and prototypes before needing to use this.

Chris

AR2 · 2012-11-22 6:20 pm

slartibartfasst said:
Hello, I'm not sure if this is the right thread for this question, but it seemed like the best so...

Does the backdoor I2S input on the SPDIF board pass the data stream directly to the I2S output or does it route the signal through the DIX9211?

I ask because the Tx on the DIX9211 appears to be limited to 216Khz whereas the USB-I2S interface I'm planning on using (Amanero) is capable of passing data in excess of that figure.

By the way, having slowly started to integrate these boards into a DAC, the SPDIF input board is a fantastic piece of equipment on its own, independent of the FIFO. The improvement over a PCM2707 (as a receiver - USB or optical SPDIF) solution previously used is immediately apparent (even using the PCM2707 as an optical transmitter). It seems the DIX9211 is in another league from the PCM2707, even with the DAC's (ESS9018) DPLL in place (as opposed to synchronous clocking).

Along with a digital volume control, having a switchable input turned my implementation into a minimalist digital pre-amp without using any uControllers; the box just boots up and is ready to go. Very convenient.

Thanks for the beautifully conceived, designed and executed SPDIF interface; I look forward to integrating the rest of your boards.

qusp said:
agreed, I dont know why more people dont grab it, its an incredible value and combined with fifo hard to really justify anything more for most occasions

i2s backdoor is direct i2s out

+1
S/PDIF board is exactly that, an exceptional value, a real digital switching preamp. If I may add, my wish / suggestion for Ian will be in next board generation to add U/FL connectors for external I2S source. Other than that, one could hardly ask for more than is already there. While I am waiting for my I2S source to implement, I am listening to optical source that never sounded as good.

hochopeper · 2012-11-23 12:00 am

hochopeper said:
One issue that has only just dawned on me is that in the Dual XO manual you refer to J12 on the FIFO board being available to be used for mute signal. You really have thought of everything already! Is anyone using this already? I haven't seen anyone asking or discussing it. However, the FIFO manual that I have saved here doesn't describe the behaviour of this output port. Maybe I'm looking at the wrong manual? What is the behaviour of this pin? Is it active high or active low, does it need an external pull up? Can this be run through isolator if i2c is not used to the dac? I was going to implement a similar mute function in my controller but if you've already done the hard work, this really might be better implemented by the FIFO directly for lower latency.

I've found what was confusing me there. There is a codependency in the manuals. The DualXO manual refers J12 on page 7, this looks like a typo or missed being updated after a design revision Ian, after reviewing the FIFO manual again it should refer to J13 port that provides indication of XFS and silence. My DAC (ES9023) needs active low input for mute, so I just need a TTL inverter and run this signal through the isolator board. I don't have i2c comms to my DAC so I will have spare pins on the general purpose isolator. The isolator also lets me convert the logic voltage to less than my DAC's AVCC.

iancanada · 2012-11-23 1:00 am

hochopeper said:
I wrote the first code for the ARM v7 + linux/python DAC/si570 controller tonight. Only ~40 lines so far, this should be fun! As a result, Ian, I wanted to cofirm something since I haven't worked with serial a great deal previously. In your protocol are you actually sending the commas? Or are you just using them to denote the separation of each hex character?

Regardless here's what I had in mind as for the custom freq definition part of the code:

Code:

#user configurable lookup, dict indices per fs ie freqmap[3] will return the index of xofreq that corresponds to desired mclk #default to 45/49MHz mclk for my ES9023 freqmap = {0: 4, 1: 5, 2: 4, 3: 5, 4: 5, 5: 4, 6: 4, 7: 5, 8: 4, 9: 5} fs = {0: '22kHz' 1: '24kHz', 2: '44.1kHz', 3: '48kHz', 4: '88kHz', 5: '96kHz', 6: '174kHz', 7: '192kHz', 8: '352kHz', 9: '384kHz'} xofreq = {0: '11.2896MHz' 1: '12.2880MHz', 2: '22.5792MHz', 3: '24.5760MHz', 4: '45.1584MHz', 5: '49.1520MHz', 6: '90.3168MHz', 7: '98.3040MHz'} def customfreq(data): string = '0xA5,OxC8,' + freqmap[data] + ',0x5A' Serial2.write(string)

NB, python code so syntax is different to C, those are comments following the '#'

Simple to use the data included with the 0xC1 command to index a frequency mapping dict that will store mclk for each fs. Code above doesn't need critique or feedback, just showing as a snapshot of what I had in mind for that part, it'll change I am sure before long.

I might start on a Web UI soon, I have time on my side with GBIII and prototypes before needing to use this.

Chris

Chris, code looks great.

Si570 driver really send all of the commands listed in my .h file

. So, to display the FIFO and clock board status, there is no any problem. But, the window time is only 100ms with 9600bps. So to control the Fs MCLK switching, I'm highly recommending using setting up USRT interrupt service to handle the communication

.

Ian

iancanada · 2012-11-23 1:03 am

AR2 said:
+1
S/PDIF board is exactly that, an exceptional value, a real digital switching preamp. If I may add, my wish / suggestion for Ian will be in next board generation to add U/FL connectors for external I2S source. Other than that, one could hardly ask for more than is already there. While I am waiting for my I2S source to implement, I am listening to optical source that never sounded as good.

That's a good idea.

Ian

necplusultra · 2012-11-23 2:06 am

Si570 interest list:

1. bigpandahk
2. tagheuer
3. hochopeper
4. qusp (of course)
5. AR2 - definitely!
6. wktk_smile
7. hirez69
8. CeeVee - you bet!
9. number9
10. analog_sa - GB maniac
11. edbk
12. atom6422
13. misterrogers - Of Course!
14. NicMac - as usual!
15. Zoran 16. PET-240
17. Coolhead
18. Slartibartfasst
19. SYklab
20. Regland
21. Neb001
22. SPWONG
23. Greg Stewart (also of course!)
24. Vitalica
25. spm
26. Fridrik
27. ccliu
28. makumba1966
29. lindamar
30. Finaxe
31. Odysseas x2
32. palmito
33. crazikid
34. deanoUK
35. Julf
36. DUC985
37.rsotirov
38.kvl
39.bkdog
40.necplusultra

hochopeper · 2012-11-23 2:57 am

Ian,

Thanks for the suggestion, I think initially I will have to just run a input loop and check for data on the serial port very quickly, python serial implementation that I am using at the moment doesn't provide interrupts or anything similar. As you've said, this will be the challenge for any undertaking to control the Si570 remotely.

Another question, are the outputs on J13 on the FIFO 5V or 3.3V logic?

Thanks,
Chris

iancanada · 2012-11-23 4:10 am

hochopeper said:
Ian,

Thanks for the suggestion, I think initially I will have to just run a input loop and check for data on the serial port very quickly, python serial implementation that I am using at the moment doesn't provide interrupts or anything similar. As you've said, this will be the challenge for any undertaking to control the Si570 remotely.

Another question, are the outputs on J13 on the FIFO 5V or 3.3V logic?

Thanks,
Chris

J13 is a 3.3V LVTTL logic. Most 5V TTL logic will tolerance with this signal.

The mute is an output, only go active(high) during Fs un-locking and frequency switching. If you have additional mute logic, your can have an 'or' logic with it

.

Please see P6 of the FIFO pdf file for more details.

Ian

hochopeper · 2012-11-23 4:13 am

iancanada said:
J13 is a 3.3V LVTTL logic. Most 5V TTL logic will tolerance with this signal.

Ian

Thanks Ian!

I was worried for the opposite reason, I have 3.3V tolerant serial port on the ARM processor that I want to interface through the isolator, so I need the 'dirty' side to run on 3.3V as 5V on these pins will damage the ARM processor.

Does the serial on the Si570 run at 3.3V also?

Chris

iancanada · 2012-11-23 4:27 am

hochopeper said:
Thanks Ian!

I was worried for the opposite reason, I have 3.3V tolerant serial port on the ARM processor that I want to interface through the isolator, so I need the 'dirty' side to run on 3.3V as 5V on these pins will damage the ARM processor.

Does the serial on the Si570 run at 3.3V also?

Chris

Yes, Si570 runs 3.3V logic also.

Ian

hochopeper · 2012-11-23 5:00 am

iancanada said:
The mute is an output, only go active(high) during Fs un-locking and frequency switching. If you have additional mute logic, your can have an 'or' logic with it .

Excellent suggestion Ian, you are always a step ahead of the rest of us. I'll include a NOR to also invert the signal for ES9023 active low input and use the other input for additional mute logic.

Also, please remember to update P7 of the DualXO manual to refer to J13 and P6 of the FIFO manual for the next GB.

Once again, thank you for your patience and assistance!
Chris

qusp · 2012-11-23 5:17 am

I thought we sorted this mistaken label out some time ago? like many months, maybe just didnt get updated.

hochopeper · 2012-11-23 5:26 am

I did a search for J12 and J13 in this thread and couldn't come up with any references to it so just pointing it out, it may have been pointed out before I started actively following this thread. Maybe it was mentioned/discussed in the GB thread, I didn't search over there yet.

Forane12 · 2012-11-23 3:40 pm

Si570 interest list:

1. bigpandahk
2. tagheuer
3. hochopeper
4. qusp (of course)
5. AR2 - definitely!
6. wktk_smile
7. hirez69
8. CeeVee - you bet!
9. number9
10. analog_sa - GB maniac
11. edbk
12. atom6422
13. misterrogers - Of Course!
14. NicMac - as usual!
15. Zoran
16. PET-240
17. Coolhead
18. Slartibartfasst
19. SYklab
20. Regland
21. Neb001
22. SPWONG
23. Greg Stewart (also of course!)
24. Vitalica
25. spm
26. Fridrik
27. ccliu
28. makumba1966
29. lindamar
30. Finaxe
31. Odysseas x2
32. palmito
33. crazikid
34. deanoUK
35. Julf
36. DUC985
37.rsotirov
38.kvl
39.bkdog
40.necplusultra
41.Nikola Krivorov X2

MisterRogers · 2012-11-23 3:44 pm

Si570 interest list:

1. bigpandahk
2. tagheuer
3. hochopeper
4. qusp (of course)
5. AR2 - definitely!
6. wktk_smile
7. hirez69
8. CeeVee - you bet!
9. number9
10. analog_sa - GB maniac
11. edbk
12. atom6422
13. misterrogers X2 - Of Course!
14. NicMac - as usual!
15. Zoran
16. PET-240
17. Coolhead
18. Slartibartfasst
19. SYklab
20. Regland
21. Neb001
22. SPWONG
23. Greg Stewart (also of course!)
24. Vitalica
25. spm
26. Fridrik
27. ccliu
28. makumba1966
29. lindamar
30. Finaxe
31. Odysseas x2
32. palmito
33. crazikid
34. deanoUK
35. Julf
36. DUC985
37.rsotirov
38.kvl
39.bkdog
40.necplusultra
41.Nikola Krivorov X2

ackcheng · 2012-11-23 3:49 pm

Hi Ian,

Will this be part of the GB3 that you meantioned on the other thread?

nvduybom · 2012-11-24 2:05 pm

Si570 interest list:

1. bigpandahk
2. tagheuer
3. hochopeper
4. qusp (of course)
5. AR2 - definitely!
6. wktk_smile
7. hirez69
8. CeeVee - you bet!
9. number9
10. analog_sa - GB maniac
11. edbk
12. atom6422
13. misterrogers X2 - Of Course!
14. NicMac - as usual!
15. Zoran
16. PET-240
17. Coolhead
18. Slartibartfasst
19. SYklab
20. Regland
21. Neb001
22. SPWONG
23. Greg Stewart (also of course!)
24. Vitalica
25. spm
26. Fridrik
27. ccliu
28. makumba1966
29. lindamar
30. Finaxe
31. Odysseas x2
32. palmito
33. crazikid
34. deanoUK
35. Julf
36. DUC985
37.rsotirov
38.kvl
39.bkdog
40.necplusultra
41.Nikola Krivorov X2
42.nvduybom

iancanada · 2012-11-24 2:12 pm

ackcheng said:
Hi Ian,

Will this be part of the GB3 that you meantioned on the other thread?

ackcheng,

It's just an interesting list so far. Si570 clock board is still under R&D.

Ian

Forane12 · 2012-11-24 3:18 pm

Is it possible that we(someone who knows how) create a thread that has all the stuff that is available, is in R&D or is waiting to get to 50pcs for a GB? 'Cause I want my name on every list

Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

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