I wish I can be half as fast as Ian is.
1, Please make sure the TTL s/pdif connections: signal to signal, gnd to gnd.
2, Please makse sure the button on the spdif board was pressed with TTL LED is lighting.
I confirmed this function without any problem by connecting to a s/pdif output of the CDROM.
Good luck.
Ian
Ian
Thanks for your reply. There is no mark on the PCB showing the polarity of the TTL input.
FIFO Latency Automatic Minimization
Hi Ian,
Would it be possible to minimize automatically the FIFO Latency (i.e. Minimize the number of PCM samples stored within the FIFO Memory) according to the sampling rate of the incoming Digital audio stream through I2S ?
The reason of my question is that I am using my DAC equipped with the FIFO to convert the audio stream of the movies I watch with my Blu Ray player. Currently the FIFO introduces roughly 2 seconds of latency between the image that is displayed and the associated movie dialogue or sound.
Thanks,
Hi Ian,
Would it be possible to minimize automatically the FIFO Latency (i.e. Minimize the number of PCM samples stored within the FIFO Memory) according to the sampling rate of the incoming Digital audio stream through I2S ?
The reason of my question is that I am using my DAC equipped with the FIFO to convert the audio stream of the movies I watch with my Blu Ray player. Currently the FIFO introduces roughly 2 seconds of latency between the image that is displayed and the associated movie dialogue or sound.
Thanks,
You'll still need a delay as your clocks will hardly be that equal to allow for very small buffers, i.e. small latency.
To me, even quite small latency is somehow irritating.
Unfortunately, my Video Player does only allow for an added delay of the sound, and not vice versa.
You need a video FIFO, a "latencizer"
To me, even quite small latency is somehow irritating.
Unfortunately, my Video Player does only allow for an added delay of the sound, and not vice versa.
You need a video FIFO, a "latencizer"
simple answer, no, the best you can do without delaying the video and still using fifo would be to upsample everything to 384khz so it doesnt take as long to fill the buffer. its part and parcel of fifo, being that its a buffer, to have a delay … Without a way to delay the video, its an unwise choice for a video system
That's very good point. Stereophiles usually don't care much about dealy around 1 second. They are more emphasized on sound quality. But home theatre application does.
Developing a variable depth FIFO algorithm with supporting by a variable frequency low jitter clock generator such as Si570 is one of the possible solutios. But the design would become more complicated. Buffering video at same time would be easier but increasing the cost. Lips control might be alternative answer.
Ian
Si570 based clock board PCB V2.0
Improvements
1. Potato GHz TTL flip-flops optimized for finial re-clock applications up to 100MHz.
2. Optional connector to introduce battery or other low noise power supply with on board LDOs bypassed.
3. Additional I2S output port with optional u.fl socket footprints at bottom side for dual mono applications.
4. Capable work with passive battery management adapter.
5. Capable interface with FIFO board via digital isolator board.
6. Providing a new serial port to communicate with potential external or third party processor sending information of MCLK frequency, *Fs and etc.
Ian
Improvements
1. Potato GHz TTL flip-flops optimized for finial re-clock applications up to 100MHz.
2. Optional connector to introduce battery or other low noise power supply with on board LDOs bypassed.
3. Additional I2S output port with optional u.fl socket footprints at bottom side for dual mono applications.
4. Capable work with passive battery management adapter.
5. Capable interface with FIFO board via digital isolator board.
6. Providing a new serial port to communicate with potential external or third party processor sending information of MCLK frequency, *Fs and etc.
Ian
Attachments
Hi Ian,
The Si570 board progress looks very promising indeed! I have two questions though and I'm not sure if either or both have been covered previously.
1. The hirose datasheet suggests removing ground plane from beneath the signal portion of the u.fl receptacle (see attached extract from hirose datasheet), it looks like your boards have the gnd continuing through this area? Is this a concern? I am far from knowledgable on these things just asking a honest question here.
2. Is it possible with the Si570 that the output stream may select a different *MCLK based on the input Fs? I have a DAC (ES9023) that I would like to use Fs*512 for Fs<=96kHz and Fs*256 for Fs>96kHz. Is this a possible configuration option via serial port? I will have either a microcontroller or an arm based linux board in the DAC enclosure so will be able to leave either of those permanently connected to the FIFO kit for 3rd party control if necessary.
The Si570 board progress looks very promising indeed! I have two questions though and I'm not sure if either or both have been covered previously.
1. The hirose datasheet suggests removing ground plane from beneath the signal portion of the u.fl receptacle (see attached extract from hirose datasheet), it looks like your boards have the gnd continuing through this area? Is this a concern? I am far from knowledgable on these things just asking a honest question here.
2. Is it possible with the Si570 that the output stream may select a different *MCLK based on the input Fs? I have a DAC (ES9023) that I would like to use Fs*512 for Fs<=96kHz and Fs*256 for Fs>96kHz. Is this a possible configuration option via serial port? I will have either a microcontroller or an arm based linux board in the DAC enclosure so will be able to leave either of those permanently connected to the FIFO kit for 3rd party control if necessary.
Attachments
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thats true it does prefer to have the ground eroded underneath to reduce capacitance, the ackodac boards have ground removed from this area. good catch mate, I hadnt noticed that before on the fifo boards. i'm sure its not a terminal error, particularly given the success of the boards, but definitely a detail worth taking care of
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The signalpart of the connector goes underneaath through that areato the central pin of the actualconnector, if the solder resist is a bit flakey it can short out. I would reccomend adding a keep out area to the actual footprint if your CAD package allows it, as it is one of those things you'll forget with this device otherwise, next time you use it! I know I have done in the past
aha so its not about messing with the bandwidth due to capacitance, but rather a safety measure? I presumed the former and thought I remembered acko saying something of the sort
restrict fail =) nvm dude I didnt notice it till afterwards either, if its not about capacitance then its nothing for a short run hand soldered board, if it is, i'm sure its not such a big deal since its being used for spdif on my board rather than i2s and its all reclocked at the dac in the portable.
nattonrice said:
restrict fail =) nvm dude I didnt notice it till afterwards either, if its not about capacitance then its nothing for a short run hand soldered board, if it is, i'm sure its not such a big deal since its being used for spdif on my board rather than i2s and its all reclocked at the dac in the portable.