Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

building up 'breadboard' for testing different options, clocks, references, regs IV etc for the dac that will drive my tweeters, the woofers are already covered with the NTD1 with another ackodac. some progress below, should power it all up tonight or tomorrow. I will try running Titan through the fifo as well as direct. it has its own clock fanout buffer and smaller fifo afaik and some rather nice clocks, so should be an interesting comparison, titan is capable of higher bandwidth than the fifo is in its current state, so i'll stick to 192 or below for the tests. the platform is normally mounted above the IV with the NTD1 thus the fairly useless set up here, though it will provide another layer of space for batteries, references etc for the rest of the testing


yes the 4 channel dac will be a 2 box affair with transformers and preregulators, battery charge circuit, along with some control circuitry in one case and the rest, DC onwards, dacs, input circuitry and output stages in the other.

its a pretty crazy build even for these 2 channels, first up i'm driving the wire BAL-BAL headphone amp directly and have altered the input circuit slightly to allow current mode coupling

please excuse the messy bench and rough and ready layout, i'll be switching things in and out so its only temporary and no thats not earwax on the cotton buds, its cardas rosin flux ;) everything is currently floating in this build too, so thats another thing i'll be optimizing with this, the analogue stages including those in the dac should have a common ground reference, but the rest can float really as its either batteries, or a dedicated secondary winding for every consumer, so we'll see. the regs on the ackodac are all choke input so they float too


dacs arent what they used to be hey? ha

Awesome!

What XO are you using now? CCHD957 22.xxxxMHz?
Did you get the 45.xxxx XO? I finished the double speed setting documant. Do you need that to configure the FIFO running ESS9018 at async mode with higher frequency MCLK?

I got the ESS9018 DAC last week, but I'm afraid I don't have time to try it until I finish upgrading the FIFO :).
 
just fired it up without headphone amp attached to confirm everything is as it should be and I get synchronous mode lock confirmation on the fifo and dac board LEDs no problem. input spdif switching works fine and it was set by default at 44.1k optical and 512fs. i'm just using it with the 100Mhz onboard crystek XO just left unpowered and a u.fl socket soldered directly to the clocks output pin and its local decoupling cap for ground, so loops should be nice and neat.

so i'm going to get some sleep and get up for first listen after soldering in the output wiring to the BAL-BAL wire as buffered IV stage. so all apears going to plan; other than the rubber rings anyway. initially i'll just test with the fifo spdif input, then i'll try titan USB->i2s->Dac. versus titan USB->i2s->Fifo->Dac

i'm just running that 22.xx crystek for now, so will be stuck with 88.2/96, I may buy the 45, or may wait till the si570 is ready, but may as well do the speed setting, or once youve set for higher speed it wont work at lower? another format I can try if possible if it will handle it, is now i have a u.fl socket directly on the 100Mhz, whether this will work as an external XO for the fifo? probably not I guess.

anyway i'll take some more pics of the setup all hooked up with the headphones tonight and post here with pics and initial listening impressions, may also send you an email to discuss finer details
cheers

looks great mate, a friend of mine remarked that my dac looks like a nuclear power plant control system ha
 
Hey Ian, just checking, you mentioned that the 2 MCLK u.fl outputs are the same clock source, but different drivers. are the 2 drivers of comparable quality? if not, which is preferred to drive the dac from and which for other consumers like the spif board or another dac?
 
Hey Ian, just checking, you mentioned that the 2 MCLK u.fl outputs are the same clock source, but different drivers. are the 2 drivers of comparable quality? if not, which is preferred to drive the dac from and which for other consumers like the spif board or another dac?

They are equal, just the different outputs of same driver. But if you really want to dig out which one is better, I'd like to say, the one closer to the driver is better, just theoretically. :)
 
Actually, the dual clock board has a reserved double speed mode which could run 45.xxxx and 49.xxxx MHz XO for ES9018 or Buffalo DAC to make us more happy, especially for the synchronized mode. I'll publish the setting document after I conformed that on a real Buffalo III dac. Maybe I still need to inquire you when I go the hookup.
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Hi Ian

I am going to order the Buffalo III and very happy to know that you've ordered it and will publish the setting document. Will you use the Trident or Salas SSLV for the power?
 
which ones? haha theres about 14 separate regs of 3 different designs, plus A123 LiFePO4 batteries in that pic and theres even more now. I suppose you mean the blue ones with AC input i'm using for preregs? if yes then thats a layout by my mate Nattonrice that he and I collaborated on the design for, as we both had similar space issues to solve on our respective ackodac builds. will take either LT1963A or LT1764A linear tech 1.5A or 3A regs (extra heatsinking required to go above ~300-400ma)
 
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Yes! thoseblue ones, i have same space issues....how to get my hands of a few of those.

I'm tired of redesigning Salas regs for specific applications, in this case for my BIII with FIFO/double clock/SPDIF interface...XMOS USBto I2S....so many regs, those nice compact ones are just what is needed.:cool:

I thought of including the SDTRANS384 but it will look like a nuclear power plant control center.....so SDTRANS is autonomous for now.
 
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haha yep sounds like you have a similar problem, bear in mind I will have roughly double this in the final 4 channel build, consisting of a bank of 20-25 of the handy blue regs as preregs for a total including the onboard on titan, fifo and beaglebone for control, for a total of ~60 regulated supplies, its nuts. I dont mind the 'technology for world domination' look, as long as I can make it look somewhat neat.

as for availability of the regs, I only have a couple spare (if that) after this build is done and not sure how many Nattonrice has left. i'll ask though, if not we could get some more as theyve proven pretty handy, shouldnt be too pricey as Golden Phoenix has the files on record now. i'll throw in for some more, how many would you need? i'd have to ask of course.

Alternatively I have an even more compact solution that also has a volumite equivalent onboard that will take the twisted pear volumite ADC DIP8, has toslink onboard complete with u.fl out, has spots for 2 x lt3032 bipolar low noise LDOs (+/-120ma and up to 20V) 1 x lt1764A/1963A adjustable, 1 x LT17643A/1963A fixed with Vsense, 1 x lt1763 adj, 1 x lt1763 fixed. it also has a battery monitor, low charge indicator and automated shutdown

if we get some, i would suggest we get a version with dc input too, or redesign this one with a score line so the rectifiers can be snapped off

anyway this is kinda on kinda off topic as its about implementing the resulting complexity us types end up with. maybe worth an entirely new thread actually, centered on managing the large networks of regulated supplies in the modern DIY DAC
 
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questions

Hello,

I'm thinking of a DAC solution for long time. First idea was AD1862 (for same good sound of a former CD player) + AD1893 (for up to 192ks/s 24 bits support) + 25.576 MHz NDK xtal oscillator (NZ2520SD for low jitter). looking forward they can't be plugged together !

It sound FIFO can be used with AD1862, instead of AD1893 without ability to change sampling rate. but can't sampling rate be adjust by player ?

reading thread some questions raised :
-Are AD1862 and PCM1704 sounds very close ? noise & linearity spec. are similar. 2R2, BiCMOS technology for both. Main difference is analog supply voltage +/-12V for AD vs +/-5V. it may easy analog part. Also Sabre specifications are impressive but it's sigma-delta with very low voltage. did you have change to hear them? what do you think?

-Also why is there oversampling in most CD player ? an extra chip is needed for. we don't have superman hearing. is it only to improve jitter (with shaper clock edge) ? or is it so that a deemphasis filter is needed for CD player. btw add analog filter pre correction like in philips SAA720 sounds good ... is it so that some FPGA have built in programmable digital filter :)-)?

thanks guys for this very informative thread :)-) !
 
-Also why is there oversampling in most CD player ? an extra chip is needed for. we don't have superman hearing. is it only to improve jitter (with shaper clock edge) ? or is it so that a deemphasis filter is needed for CD player. btw add analog filter pre correction like in philips SAA720 sounds good ... is it so that some FPGA have built in programmable digital filter :)-)? thanks guys for this very informative thread :)-) !

Oversampling moves the ultrasonic image replications higher in frequency by a factor equal to the oversampling ratio. The greatly eases the demands on the analog output filter. It does not increase resolution, nor extend the high frequency response, nor reduce jitter, nor does it have anything to do with de-emphasis.

Programmable digital filters, whether in FPGA, DSP, or application specific chips enable CD-player/DAC designers to implement proprietary filter responses rather than be limited to the few choices available in most DAC chips.
 
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Just Looking

Hey All,

Looking to integrate this on a TDA1541 and a Buff III.

waiting to hear integration as both are to be completed as yet. Have waveIO on way too, so hopefully qusp, we can get together and hear the differences between Titan and wave.

Looking forward to your results!

Cheers,

Drew.
 
Hi all,

Thank you for up sampling explanations. but ??? isn't it so that ultrasonic images can't be hear ? are they harmful ones in amplifiers due to linearity issues (intermodulations makes ultrasonic alias to signal) ?
Also i wonder about 24 to 20 bit conversion, removing LSB sound OK. But is there some signal processing trick, because dither is used in some chips ?

have a nice week end !!
 
Hello,

reading thread some questions raised :
-Are AD1862 and PCM1704 sounds very close ? noise & linearity spec. are similar. 2R2, BiCMOS technology for both. Main difference is analog supply voltage +/-12V for AD vs +/-5V. it may easy analog part. !

IMHO and many others the AD1862 and the PMC1704 represent the pinnacle of digital audio technology, all audio models following have used a very different cheaper to manufacture technology which just plain sound different.

I think this latest revision of the fifo allows one to "plug directly into a left and right PCM1704 or AD1862, which in the past has involved sound degrading glue logic or a hard coded oversampling chip prior to the dac chip. The silicon in wire oversampling chips never made it to the level needed to go beyond rbcd (DF1704/6 have a terrible impulse response and frankly sound wrong), then the proprietary blackfin/sharc dsp that followed aren't DIY pieces.

So this will be a major shift in ability to use these BB and AD crowning achievement DAC chips, some creative computer oversampling (we do need to find a modern apodizing 8x oversampling VST for foobar)
and/or analog filter will be needed but this is all DIY attainable.

This latest fifo has the potential to compete with the worlds best D/AC's without spending 5 figures.
If you are interested read up on the Phasure, similiar concept except not DIY and very expensive.

Then also for the NOS folks this also opens up possibilities to use good chips like the PCM56k or AD1865K without the dreaded channel mismatch. These chips are unique over the standard TDA1541 in that they allow very elagent analog stages due to the ability to deal with high voltage compliance on the output.

Last most important it allows the DAC to have a true masterclock without crazy jitter inducing isolators or being tied to a SDtransport.

All in all my opinion is to get on the bus before this thing goes commercial integrated into a $5k D/AC.
 
Hi all,

Thank you for up sampling explanations. but ??? isn't it so that ultrasonic images can't be hear ? are they harmful ones in amplifiers due to linearity issues (intermodulations makes ultrasonic alias to signal) ?
Also i wonder about 24 to 20 bit conversion, removing LSB sound OK. But is there some signal processing trick, because dither is used in some chips ?

have a nice week end !!

Correct, the ultrasonic images cannot be heard directly. Whether or not they can be heard indirectly as a product of amplifier intermodulation distortion depends on your amplifier. All discrete amplitude level D/A converter chips produce ultrasonic images of the desired signal, whether they use oversampling or not. Oversampling simply enables a more effective suppression of ultrasonic noise/image energy by moving such images greatly higher in frequency.

Aliasing is only a concern if the digital filtering is inadequately sharp, which means that non-oversampling (no digital filter) DACs are far more susceptable to aliasing then are oversampling DACs.

Regarding bit-length reduction, spectrally shaped dither is commonly utilized to randomize distortion resulting from simple truncation (chopping off) of the LSBs. The DAC noise floor is increased in exchange for a reduced THD, an engineering trade-off which is particulalry apparent as the signal level falls.

I hope that I correctly understood and addressed your questions. :)
 
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Finish upgrading FIFO board from V3.33 to V3.80

Upgrading job finished finally. Two weekends were killedJ. New version will include the following features:

1. Optional 32bit left-justified output format support
Reason of this feature: To integrate FIFO with some DSPs or DACs which do not accept I2S input, for example, PMD100, SM5842, SM5843…

2. Optional 16-32bit left-justified input format support
Optional 16bit right-justified input format support
Optional 24bit right-justified input format support
Reason of these features: To interface FIFO with some digital audio frontend which do not output I2S. For example, interfacing with some DIRs from Japanese manufacturers, tapping signals form CDROM…

3. New optional default 512*Fs MCLK support
Only Single XO clock board user will benefit from this feature. Dual XO clock board will take over all the default *Fs settings.
Reason of this feature: Single XO clock board users will have more options to select frequencies. For examples, use 22.5792MHz oscillator for 44.1KHz Fs or 24.5760Mhz for 48Khz, and so on. And same XO will work for 88.2Khz or 96Khz either, just a jumper! :).

All new features are jumper selectable. Only FPGA/CPLD firmware is involved in this upgrading. Hardware keeps no change. If you are happy with I2S and don’t need these new features, then you don’t need making any upgrading. Performance didn’t change any.

Testing FPGA board was upgraded at same time to perform loop test.

I attached the waveform of new support formats just for reference.

Have a good night.
 

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Ian,

I'm still getting my head around the first setup, let us know how you go with B III!
How far off is the GB quantity?
Thanks again!

Hi PET-240

Wktk_smile hooked up FIFO with BII :
http://www.diyaudio.com/forums/digital-line-level/192465-asynchronous-i2s-fifo-project-ultimate-weapon-fight-jitter-42.html#post2993060

And, Qusp is working with another ESS9018 DAC
http://www.diyaudio.com/forums/digital-line-level/192465-asynchronous-i2s-fifo-project-ultimate-weapon-fight-jitter-44.html#post2998719

I’ll start BIII hookup next week. Will post the result.

The upgrading was promised for the GB II. So it should be very soon.
 
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Hi Ian,

Nice work and thank you for sacrificing two weekends (at least) for hobby - with a full time job and family I know this is hard :)

I plan to try different digital filters before my AD1865 and will start with DF1704 as that is the easiest to interface with my current setup and FIFO as it supports LVTTL and has I2S input. I would also like to try SM5842(7) and/or PMD100 so I will need the Left Justified output support as well.

Others might have asked: can existing FIFOs be upgraded with your new firmware? You are probably using JTAG for this, for ~15$ there are plenty of AVR JTAG programmers on ebay.

Thank you,
Zsolt