Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 88 - diyAudio
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Old 21st August 2012, 12:15 AM   #871
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Default I2S to PCM convertor daughter board driving NOS DACs: AD1865/62, PCM1704/02, TDA1541

I assembled this daughter board and uploaded the FW last weekend. It starts to work now. I’m busy doing the testing and verification jobs. Finial evaluations will be made by volunteers later on.

Simulation results show that the Fmax of MCLK could go up to 125MHz. All loop tests will be down under 100MHz clock testing condition which equal to 390.625 KHz Fs if MCLK=256Fs.

This daughter board was designed to stack above the clock board of the FIFO KIT. It could work with both Single XO clock board and Dual XO clock board. It need I2S and MCLK inputs, and will output optimized PCM timing which can drive those NOS DACs (or DSP) directly. It has an independent power input port. Power could be fed from FIFO KIT or a stand along 5V DC power supply.

Different from previous discrete logic designs, all of the logics now become 100% synchronized design inside FPGA/CPLD. That means the final phase noise performance will be decided only by the MCLK. It doesn’t care much about the input I2S signals if those signals are correct.

GHz TTL Potato FF was introduced for the last re-clock stage to boost the performance because all of the PCM clocks are generated clock.

The current design has been revised to a universal I2S to PCM convertor. It could interface not only with FIFO KIT but also with all kinds of I2S sources.

I’m still struggling if to open a new thread to discuss detail issues and applications of this project. NOS fans and DS fans are belong to different group.

Ian
Attached Images
File Type: jpg PCMdaughterBoard1.JPG (452.2 KB, 601 views)
File Type: jpg PCMdaughterBoard2.JPG (414.7 KB, 580 views)
File Type: jpg StackWithFIFO1.JPG (462.3 KB, 558 views)
File Type: jpg StackWithFIFO2.JPG (424.4 KB, 538 views)
File Type: jpg StackWithFIFO3.JPG (440.2 KB, 526 views)
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Last edited by iancanada; 21st August 2012 at 12:20 AM.
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Old 21st August 2012, 07:41 AM   #872
marce is offline marce  United Kingdom
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I have a full SIV (signal Integrity Verify) system as part of my CAD software setup for PCB design, when I get chance I will simulate some standard signals we are likely to see in the area we are working in, I can then simulate the wave forms with and without probes. (I have already done this and have asked to publish the data, but have not been allowed yet, for a JTAG clock at 12MHz).
The 13GHz scope was obtained because of the DDR 1/2/3 memory interface, he engineers where having trouble with a DDR2 interface and scope shots were not matching up with the similations (250MHz and 4GHz scopes) so the faster scope was purchased to improve things, this initially didn't work untill we started looking at scope probes and moddelling them.
The main problem is not ultimate clock speeds but the ever increasing rise times, this has two effects, one the scope probe will attenuate theigh frequency content making the rising and falling edges look more gentle than they are are more critical: they can attenuate ringing caused by the high rise times, I have seen circuits that work when probed as the loading of the scope acts as a termination then stop working when the scope was removed.
When I get back to my base office (currently in London) I am going to be looking more at SIV and the new tools we have available (SIVis one, but also now got PIA:
http://www.quadrasol.co.uk/useruploa...1_10_05.pdf)so will be doing a project to illustrate using the tools and more importantley how they equate to real world situations, and how the simulations map to real world measured results (as we are finding that first timeusers suffer fromthe same problems we did, ie what you so was different on screen than the scope).The simulation software can also do signals between boards, but apart from training sessions I havn't moddelled that in reallife apart from SPDIFF signals down ever longer runs of cables about a year ago. Your Altera board would be a good design to play with, not many parts (less IBIS files to source) and reasonably simple to set up
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Old 22nd August 2012, 10:57 AM   #873
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When a saw the rise time problem on the picture I taught the same thing, I'm using a active probe with my scope would not go back to capacitive probe for fine detail signal work. for example the Tektronix Oscilloscope P6243 1GHz 10X is about 200$-300$ on ebay, always check the working voltage of these probes because they can be somewhat low 15volt on cheaper models 35-40volts is best. Static is also a issue.

Would recommend it for any serious diyAudio enthusiasm.On sunny days I even probe without the ground clip
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Old 25th August 2012, 02:26 PM   #874
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Hi all.
iancanada you have a very outstanding design.
I would appreciate if you briefly explain how the FIFO working, if it is not a secret.
Usually, for receiving asynchronous data, used VCXO oscillator.
Ie FIFO usually works with a VC oscillator and buffers data until the osc tune frequency.
If frequency osc is constant, then what happen if input clock frequensy lower than output clock? (Contain fully audio track in buffer will be very long).

Sorry for my English.
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Old 25th August 2012, 04:08 PM   #875
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Quote:
Originally Posted by Dortonyan View Post
Hi all.
iancanada you have a very outstanding design.
I would appreciate if you briefly explain how the FIFO working, if it is not a secret.
Usually, for receiving asynchronous data, used VCXO oscillator.
Ie FIFO usually works with a VC oscillator and buffers data until the osc tune frequency.
If frequency osc is constant, then what happen if input clock frequensy lower than output clock? (Contain fully audio track in buffer will be very long).

Sorry for my English.
Thanks Dortonyan for your question, hope some help :

"The digital audio stream consists of two parts: data and clock. Usually we donít have any problem with data. But the clock is not perfect (there is no ideal clock in the real world); it comes with jitter (or phase noise). Jitter is the main reason why different digital audio sources sound different even when they play the same audio stream.

An asynchronous I2S FIFO is a kind of logic device which can buffer the digital audio stream, allowing the audio data to pass through but isolating the original clock and replacing it with a new one (secondary clock). If the new clock has less phase noise than the old one, the digital audio stream after the FIFO will have less jitter and that will make the DAC or other digital audio device playing the stream sound better. Moreover, the sound quality of the playback will be independent from the digital audio source. So, together with clock technology, the I2S FIFO is firmly believed to be one of the most effective solutions to deal with jitter."

Ian
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Old 25th August 2012, 04:48 PM   #876
Julf is offline Julf  Europe
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Ian,

Quote:
Originally Posted by iancanada View Post
An asynchronous I2S FIFO is a kind of logic device which can buffer the digital audio stream, allowing the audio data to pass through but isolating the original clock and replacing it with a new one (secondary clock).
I think Dortonyan was specifically interested in what happens when the input clock rate is consistently slower than the FIFO output clock rate. Assuming you start with the buffer half full or full, you will still eventually underflow (run out of data in the FIFO), right?
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Old 25th August 2012, 07:36 PM   #877
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Thanks iancanada, once again read and understood.
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Old 26th August 2012, 01:58 PM   #878
ggking7 is offline ggking7  United States
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I just stumbled upon this thread and it looks very interesting. Will this device be for sale? Would it be installed between the computer and DAC? Or maybe soldered into the DAC?

I'm sorry for the basic questions but I'm just a wannabe DIY guy. You all are leading the way.
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Old 26th August 2012, 02:29 PM   #879
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Quote:
Originally Posted by ggking7 View Post
I just stumbled upon this thread and it looks very interesting. Will this device be for sale? Would it be installed between the computer and DAC? Or maybe soldered into the DAC?

I'm sorry for the basic questions but I'm just a wannabe DIY guy. You all are leading the way.
Yes, you ard right. If everything be integrated into a device as a spdif FIFO , that would be a very good news for PC HIFI. A PC based player will be boosted into transport level if it you place it between PC and DAC.

Ian
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Old 26th August 2012, 04:24 PM   #880
ggking7 is offline ggking7  United States
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OK, so this will not available as a standalone device? It must be soldered into a DAC by a manufacturer or DIYer?
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