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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
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Old 10th August 2012, 04:02 AM   #841
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by roger57 View Post
Excellent numbers. I think the versatility of this board would be an equitable trade for the difference in phase noise. Those numbers certainly better than any of the typical 11.2M XO's.
I Agree.

Actually there is another programmble XO from SiLabs, Si598. It's pin to pin compatible with Si570, only lower grade on phase noise performance, as well as the price. They sent me samples of both. Si570 sounds much better than the other one, very obviously. I think the main difference is the internal crystal. that's the reason I didn't use Si598.

You can find the documents form SiLabs website.

Have a good night.

Ian

Last edited by iancanada; 10th August 2012 at 04:04 AM.
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Old 10th August 2012, 05:59 PM   #842
qusp is offline qusp  Australia
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Quote:
Originally Posted by iancanada View Post
.........Si570....... CCHD957
10- Hz N/A .........-97dB
100Hz -112dB ....-126dB
1-KHz -122dB ....-148dB
10KHz -132dB ....-162dB
100KHz -137dB ...-171dB
1-Mhz -144dB .....-170dB
10Mhz -150dB ......N/A
100Mhz N/A .........N/A
excellent! man seriously, whats not to like given all the trade-offs any other way? you know my feelings Ian! the Sydney headfi meet is next weekend, I had planned to send the boards back to you for update in time to get them back for the meet, but my Mother has been quite ill, she went in for neuro surgery today, all went well thankfully, but its certainly been a source of distraction lately.

Anyway after the meet i'll send it back for update and may be good timing by the time it gets there in 3-4 weeks for you to send back together.

Quote:
Originally Posted by roger57 View Post
Excellent numbers. I think the versatility of this board would be an equitable trade for the difference in phase noise. Those numbers certainly better than any of the typical 11.2M XO's.
fully agreed here!
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Old 10th August 2012, 06:04 PM   #843
qusp is offline qusp  Australia
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Ian, can I make a request mate? any chance of supplying a few duplicate Sdata outs? this way we ess users or others of similar type, can feed pin 55-58 directly for the full 6 bit quantizer and full output levels/DNR rather than simply copying with jumpers etc (not easy to do neatly on the ackodac board directly). I suppose I could use one of the adapter PCBs with some foil soldered across the outputs to duplicate it neatly. do you know what i'm getting at? maybe the second option is best, then I can just wait it out for the multichannel to eventuate (not hassling, got plenty on my plate)

Last edited by qusp; 10th August 2012 at 06:07 PM.
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Old 10th August 2012, 11:25 PM   #844
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by qusp View Post
Ian, can I make a request mate? any chance of supplying a few duplicate Sdata outs? this way we ess users or others of similar type, can feed pin 55-58 directly for the full 6 bit quantizer and full output levels/DNR rather than simply copying with jumpers etc (not easy to do neatly on the ackodac board directly). I suppose I could use one of the adapter PCBs with some foil soldered across the outputs to duplicate it neatly. do you know what i'm getting at? maybe the second option is best, then I can just wait it out for the multichannel to eventuate (not hassling, got plenty on my plate)
Didn't get what you want . You may still need update the FIFO and the Dual XO to use your 45.xxx and 49.xxx low jitter CCHD. They are better than the 22.xxx and 24.xxx for ESS DAC at sync mode. With async mode, should be no problem.

Hope every thing is well with your mom. All my best wish.

Ian
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Old 11th August 2012, 02:43 AM   #845
qusp is offline qusp  Australia
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oh i'll still be sending it back for the update, in sync mode the lower speed clocks are somewhat unreliable and can cause glitches with the ESS and without the ability for the dac chip to know a glitch is happening and mute the clocks + outputs; these glitches are not good at all.

what I mean is, with ESS its best to copy the SDATA signal to all of the PCM data inputs (pin 55-58), so all 8 dacs internally are fed the signal to each dac cell. it needs this for proper output levels and best performance. on BII these inputs are routed in such a way as to combine with the register setting to just copy the same input signal to all the pins (if you test with DMM across pins 55-58 with PCM input selected there is continuity), on BIII you have to do this with jumpers for stereo mode, or 4 channel, mono etc. this is the case for both es9018 and es9012, strangely enough. this applies for DSD as well, except there is then 8 pins plus frame clock. for spdif this routing is all done internally.

is that better? if not let me know, but i'll take it to email.

thanks for the well wishes mate, much appreciated
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Old 12th August 2012, 06:18 AM   #846
bigpandahk is offline bigpandahk  Hong Kong
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Hi Ian

Just soldering the XO and BIII adaptors, both adaptors have pads for decoupling caps. and you have included some caps with the XO adaptor. Could you advise where should I put those caps? With caps on the XO adaptor, should I put caps on the BIII adaptor too and what are the values?

Thanks
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Old 12th August 2012, 01:24 PM   #847
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by bigpandahk View Post
Hi Ian

Just soldering the XO and BIII adaptors, both adaptors have pads for decoupling caps. and you have included some caps with the XO adaptor. Could you advise where should I put those caps? With caps on the XO adaptor, should I put caps on the BIII adaptor too and what are the values?

Thanks
Universal SMT XO adapter
"Two optional 100n 0603 and one 1u 0805 MLCC are recommended. But if the XO has good internal decoupling capacitors, then you don’t need any of them."
PN: 445-1316-2-ND, 490-4785-1-ND

BIII SYNC/ASYNC clock adapter, optional capacitors:
2X100n 0603 MLCC: 445-1316-2-ND

Please download the techincal PDF files related to below the GB II poste.

Ian

Last edited by iancanada; 12th August 2012 at 01:27 PM.
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Old 12th August 2012, 10:06 PM   #848
Rosendorfer is offline Rosendorfer  Poland
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Hi Ian

Small curiosity R&D question:
Why there is no u.FL sockets at input of Clock board ?
There are everywhere at all inputs and outputs of Your boards but not at input of Clock Board, so connection between FIFO and Clock can't be done by u.FL cables.
Just wonder about the reason.

Jitter Free Music is Playing .....

Rosendorfer
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Old 13th August 2012, 02:37 AM   #849
regal is offline regal  United States
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Quote:
Originally Posted by Rosendorfer View Post
Hi Ian

Small curiosity R&D question:
Why there is no u.FL sockets at input of Clock board ?
There are everywhere at all inputs and outputs of Your boards but not at input of Clock Board, so connection between FIFO and Clock can't be done by u.FL cables.
Just wonder about the reason.

Jitter Free Music is Playing .....

Rosendorfer
The clock board aligns the I2S output of the Fifo processor to the quality audio clock, so any conceivable impedance match issue prior to that is going to be corrected by the reclock.
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Old 13th August 2012, 11:36 AM   #850
Rosendorfer is offline Rosendorfer  Poland
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Quote:
Originally Posted by regal View Post
The clock board aligns the I2S output of the Fifo processor to the quality audio clock, so any conceivable impedance match issue prior to that is going to be corrected by the reclock.
Hi Regal

Not that I disagree this is of cause true, but as far as I know, the same could be told about connection from Spidf to FIFO as this as well will be:"corrected by the reclock" and there Ian is using u.FL.
Well more..... there are u.FL sockets ready waiting at output of FIFO board that when connecting FIFI to Clock Board, just cannot be used because of lack of u.FL inputs at Clock board input.

Rosendorfer
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