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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
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Old 5th July 2012, 08:49 AM   #741
lwif is offline lwif
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Hi Ian,

Ok, thanks for your answer. That's seems I will try this way (I will add an spdif board).
That is really nice to find all this good documentation.
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Old 5th July 2012, 09:24 AM   #742
PET240 is offline PET240  Australia
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Quote:
Originally Posted by qusp View Post
Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter-wrath-jpg

haha

actually i'm making an order at mouser tonight or tomorrow if you want me to add it

Hey qusp,

Appreciate it, you have my email, let me know!

Thanks Muchly!

Drew.
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Old 7th July 2012, 01:55 AM   #743
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Default BIII U.FL input adapter testing

Because of the internal ASRC architecture, Sabre ESS DACs are quite sensitive to the jitter from the input signals. Both async mode and sync mode are. I like this adapter. Itís kind of perfect solution to introduce higher quality U.FL connectors into BIII DAC. But still not as good as DAC which comes with U.FL sockets originally placed on the PCB.

I did some test with this new adapter on my BIII yesterday. It works very well. Iíve noticed some improvement: With BIII (DPLL bandwidth set to lowest) working with I2S FIFO at SYNC mode, If feeding signals with this adapter and U.FL cables, DPLL locks solid never lost; However, without this adapter and U.FL cables, it will lost lock occasionally(every 10 minutes roughly).

The BIII input adapter has 9 U.FL footprints, can support all modes: Multi-S/PDIF, Stereo I2S, Multi-channel I2S, or multi-channel DSD.

I attached some pictures below just show how the adapter works. Actually the BIII input adapter and the clock adapter were integrated into one PCB. So usually, they come as a set. Iíll supply each FIFO user from GB II one set PCB for free. But to assemble them perfectly is a challenge.

Ian
Attached Images
File Type: jpg InputAdapter1.JPG (316.8 KB, 1286 views)
File Type: jpg InputAdapter2.JPG (358.7 KB, 1256 views)
File Type: jpg U.FLadapterWorking.JPG (391.6 KB, 4706 views)
File Type: jpg InputU.FLadapter2.JPG (421.1 KB, 4753 views)
File Type: jpg AdapterPCB.JPG (478.2 KB, 568 views)
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Old 7th July 2012, 02:58 AM   #744
qusp is offline qusp  Australia
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looks good Ian, yep, native u.fl/w.fl connection ftw! i'll have to buy one maybe 2 from you if you dont mind
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Old 7th July 2012, 02:58 AM   #745
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Default Test of BIII clock adapter with ASYNC and SYNC mode

BIII didn’t design with SYNC mode originally. But with this small adapter, it can now. Thanks for the backdoor under the original XO footprint.

Assemble the adapter first. Then remove the CCHD950 from BIII PCB. Solder the three pins of the clock adapter into CLOCK, GND and VDD_XO on the BIII PCB. That’s all. The assembly looks pretty nice.

With U.FL cable connected to the external clock from FIFO clock board and onboard XO removed from the socket, ESS9018 works at SYNC mode; while with on board 100MHz CCHD950 plugged into the socket and external U.FL clock cable disconnected, it works at ASYNC mode. So, having this small BIII clock adapter, it will be very easy to switch between ASYNC and SYNC mode. So, different modes with different clocks will be experienced and a lot of researching and comparing are waiting.

Please see the pictures below for the configuration and details. Please note the name of pictures for the meanings.
Attached Images
File Type: jpg BIIIclockAdapter1.JPG (337.5 KB, 532 views)
File Type: jpg BIIIclockAdapter2.JPG (316.6 KB, 339 views)
File Type: jpg RemoveCCHD950.JPG (738.8 KB, 435 views)
File Type: jpg SyncMode.JPG (465.0 KB, 497 views)
File Type: jpg AsyncMode.JPG (398.6 KB, 485 views)
File Type: jpg Sync_Async_clock.JPG (260.3 KB, 463 views)
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Old 7th July 2012, 03:02 AM   #746
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by qusp View Post
looks good Ian, yep, native u.fl/w.fl connection ftw! i'll have to buy one maybe 2 from you if you dont mind
Yes, it really good. Much better then the DIP connectors I used before. Signals improved obviously.

Ian
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Old 7th July 2012, 03:13 AM   #747
qusp is offline qusp  Australia
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now you just need ackodac and forget adapters

it was interesting to hear it confirmed your simple experiment showing unlocks every ~10mins before adapter and no unlocks after, very simple demonstration. your adapter is great, brings this signal integrity to those with BIII..almost

Last edited by qusp; 7th July 2012 at 03:16 AM.
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Old 7th July 2012, 03:18 AM   #748
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by qusp View Post
now you just need ackodac and forget adapters
I hope so, as well as the D1 IV .
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Old 7th July 2012, 03:28 AM   #749
qusp is offline qusp  Australia
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indeed, it surely must be in production now. i'm looking forward to drawing a line under the dac project for a while after I build the second D1 and focus on speakers
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Old 7th July 2012, 08:19 AM   #750
soundcheck is offline soundcheck  Germany
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Ian.

Why don't you built a DAC by yourself?

Instead of tweaking an average 3rd party product you should built your own DAC.

It's just a PIC and a DAC on top of your stuff. Shouldn't be such a big problem for you.
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