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Old 19th August 2011, 06:46 AM   #61
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Originally Posted by iancanada View Post

If you took a close look at the pictures, you may find out, at the clock section, I have different design idea. My design idea on the clock board is kind of open concept... Comparing with the benefit it brought, that MCU is worth it. To keeping bring the Ďfuní, Iíll design series of clock boards, this is only the first one.
Thanks for the explanation. I now understand. The difference between our approaches is that I chose to implement the switch control functions in the main FPGA, be it PLL or DDS or blunt switching.

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On the other hand, my I2S FIFO is working at slave mode; the clock board is the master device with highest priority. All of signals are generated by the clock board at finial stage in order to get the better jitter performance. I donít think using a slave device to dominate the master frequency control is a good idea. Sorry, at this point, I couldnít agree with you.
I agree that during normal operation, the FIFO is in slave mode, but when the input sample rate changes, the clock has to change asap to avoid missing input data, otherwise the FIFO will overflow/underflow in no time, or gives out pitch shifted output, fun but not really HiFi. If the FIFO chip is also responsible for detecting the sample rate changes, it needs to *dominate* the frequency selection, if you prefer that word.

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Talking about the relay, I couldnít find anything more suitable for this double XO configuration other than it, unless you power and run the two XOs at same time which is the way I donít like. Comparing with FPGA and other logic switching circuit, to switch between clocks, the relay almost introduces no additive jitter. That was the reason I use it. Yes you are right, some of the relays may not suitable for switching the clock, but not include the one I selected. You may notice the good high frequency performance from the insertion loss plot I attached (below 0.1dB at 20 Mhz, below 0.8dB at 1 GHz). Regarding to the impedance match, of course, the dedicated RF relay comes with better performance. But how much we could gain from it? Just let me figure it out. The RF relay could be considered as a half inch cable which we could hookup the source terminate resistor Rs before, while, the non-RF relay could be considered as a half inch lead which we have to hookup the Rs after. The only difference in between is without or with that half inch of additional lead on the XO output pin. For the MCLK up to 24.5760 Mhz with 1-3ns raising/falling time, I donít see that half inch will make big difference on the output jitter performance. But anyway, if have chance, Iíd like to try the RF relay to confirm this matter.
I'm confused. I assume that you use the relay to switch the clock, thus the claim that the relay almost introduces no additive jitter. But you also say that you don't like running two XOs at the same time. Do you only switch one of the XOs on at any time?

In my work experience, a half-inch wire on a 24.576MHz clock can easily make a "good citizen" electronics product into a piece of crap, in terms of FCC compliance.

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About the switching time, thank you for the noticing. I may have some idea to make it shorter. The only thing I have to compromise with is the frequencies detection accuracy which may influence the performance of the synthesizer based clock board I might design later on. Fortunately, Fs changing only happen at the moment when people switching the source but not the moment when it was playing.
Fs could also change on-the-fly, for example, in a Foobar 2000 playlist of mixed sample rate files. You don't want to miss the first couple of seconds of the new song.

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Just hope you could re-start your project. I believe different idea may suitable for different platform. Ian
Me, too, and I'm very glad to have the opportunity to discuss with you on these topics. More importantly, I think, we can learn different ideas from each other here.
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Old 19th August 2011, 09:33 AM   #62
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and the new low jitter clock has 10ps jitter, the reclock flip-flop has 20ps additive jitter
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and you get 30ps jitter on I2S signals
no, only 22.36ps
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Old 19th August 2011, 09:37 AM   #63
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and flipflops have only a few ps RMS jitter depending on series (HC,AC,ABT etc) and PSU
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Old 20th August 2011, 04:00 AM   #64
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Originally Posted by Nazar_lv View Post
no, only 22.36ps
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Originally Posted by Nazar_lv View Post
and flipflops have only a few ps RMS jitter depending on series (HC,AC,ABT etc) and PSU
Hi Nazar_lv. Thank you so much for the more accurate calculation on the RMS jitter(your are right, should be the root of the square sum), as well as the good news about the flip-flop jitter.
Regarding to this issue, at least three times, I inquired to the FAE from TI, each time, I got the same answer: we don't have any jitter data for those devices, even one time, I talked with them face to face on a techincal meeting. And their suggestion was 'do not use flip-flop generate significant clock signal, use pll' .
I remember the new AUC series flip-flop comes with highest Fmax, and only once, I found its jitter data from a website, if I'm not wrong, it was 9ps, but unfortunately I couldn't find it out again.
Where your data comes from? Could you let me know a bit detail about those data? Have a nice weekend. Ian

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Old 20th August 2011, 03:43 PM   #65
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Hi Ian, jitter data is from much documents and some friends, some of them were at my site (now hacked)
In attach phase noise plot from McClure Residual phase noise in digital frequency dividers
24MHz/4
as you see for old LS series Phase jitter is only 0.12pS RMS but all this is very dependent from PSU noise (for CMOS devices especially)

Regards,
Nazar
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Old 22nd August 2011, 10:54 PM   #66
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Fs could also change on-the-fly, for example, in a Foobar 2000 playlist of mixed sample rate files. You don't want to miss the first couple of seconds of the new song.
Good point. I'v got some idea to speed up the switching state machine. Many thanks .
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Old 24th August 2011, 01:28 PM   #67
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Originally Posted by Nazar_lv View Post
Hi Ian, jitter data is from much documents and some friends, some of them were at my site (now hacked)
In attach phase noise plot from McClure Residual phase noise in digital frequency dividers
24MHz/4
as you see for old LS series Phase jitter is only 0.12pS RMS but all this is very dependent from PSU noise (for CMOS devices especially)
Nazar
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Originally Posted by -ecdesigns- View Post
Then there are practical hardware limitations that spoil the fun. Even DAC chips need logic building blocks like gates and flip-flops.

Simple D flip-flops used for on-chip latching, (synchronous) reclocking or (synchronous) dividers add extra jitter. Here are some examples that illustrate the problem:

CD4013 (CMOS), 325ps
74HCT74, 75ps
74LS74, 65ps
74F74, 26ps
NC7SZ175P6, 13ps
SN74AUC1G80, 9ps
NC7SV74K8X, 5ps
MC100EP52DTG, 1.6ps

1.6ps is about as low as it gets using (P)ECL. But most DAC chips are based CMOS logic, resulting in estimated jitter levels between approx. 5ps and 75ps.
Hi Nazar, I found out that flip-flop jitter data from this website finally. But it seems the result is quite different from what you provided. Which one is more close to the real case?
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Old 24th August 2011, 06:28 PM   #68
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Here is a potential alternative for fast low noise SSI logic Potato Semiconductor / The GHz TTL/ CMOS IO Interface Logic/ Potato IC The stuff really works and meets the specs, probably better than the specs. And the parts are available from eBay!?? Its unusual to see a semi startup that is so low profile.

Be careful about the common jitter numbers you see published, even by very responsible manufacturers. They are probably correct but usually meaningless for audio. The normal spec is jitter in a 12 KHz to 20 MHz band. This is nice but mostly not going to affect an audio band DAC (or ADC for that matter). The AES has a spec that I think is too conservative, using 100 Hz to 40 KHz as far as I can remember.

Background- the usual jitter spec is for SONET applications for high speed data communications. This has very little to do with audio. The jitter above the sample frequency has no where to go so it can really be ignored. If its mixed with a signal (audio) the IM products are above the reconstruction filter. What happens in an oversampled DAC is a bit harder to imagine but its still probably not an issue. However the low frequency is where the jitter lies anyway. The jitter is derived from the phase noise plot. There are a number of calculators on the web that make this pretty easy. Converts an oscillator phase noise curve to jitter information Looking at the phase noise plots you will see that they all rise a lot at low frequencies. There is some literature that discounts the audibility of low frequency jitter (that why AES stopped at 100 Hz) but I don't really buy that.

The low frequency increase is the nature of a crystal oscillator (or any oscillator) but it can be made much worse with power supply noise. Measuring this is not real easy. Measuring at the state of the art is really difficult. I would be very cautious about spending real money (more than $20) on an oscillator without real verifiable phase noise plots, and especially with a single jitter number.

I would look at jitter in a 10 Hz to 200 KHz band. Below 10 Hz is problematic to get good measurements on and hard to say if it matters. Above 200 KHz will be above the highest common sample rate (192 KHz) Obviously frequency accuracy of any decent oscillator will be way below audibility. I am at a loss on the fascination with rubidium oscillators for audio. They are expensive, take a long time to warm up and don't run at audio frequencies. The ones that "do" use either a DDC or a PLL to steer a crystal oscillator. This is all a good solution for the wrong problem.

Another not well understood issue is the affect the load can have on a crystal oscillator. For measurements they usually use a distribution amp with a very high reverse isolation (150 dB) to prevent the oscillator under test interacting with the reference. This would also be very important for a good audio clock.

And the start up time and retrace of a crystal should be understood. A good oscillator actually takes a while to stabilize. usually the specs are not guaranteed until the oscillator has run for a period, like 24 hours. Some really take weeks or months before they have really settled. Switching oscillators on and off between tracks may really compromise their performance.

Here is a calculator that will put some perspective on this Jitter Calculator Also keep in mind that even the best DAC chips we work with are not good much beyond 22 bits. The rest is really little more than noise.

I have been working on ways to measure jitter (more accessible than a commercial phase noise test set) and power supply noise at very low levels. Both are real engineering problems and will limit progress on low jitter oscillator development if not overcome. Once I know they really work I'll publish the how to but I don't want to waste anyone else's time with dead-ends. I have wasted a lot of my own with those.
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Old 24th August 2011, 07:12 PM   #69
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I am at a loss on the fascination with rubidium oscillators for audio. They are expensive, take a long time to warm up and don't run at audio frequencies. The ones that "do" use either a DDC or a PLL to steer a crystal oscillator. This is all a good solution for the wrong problem.
Even the ones that don't output at digital audio clock frequencies use both FLL and DDS inside. But the VCXO inside is usually well built and the DDS has low residual phase noise. Overall speaking, it may not be as bad as the off-the-shelf oscillators. At least the manufacturer gives you a typical phase noise plot, which is usually not available for the off-the-shelf oscillators.
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Old 25th August 2011, 03:08 AM   #70
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Once you get deep into this stuff dds (what I meant to say earlier) isn't perfect and can have some unfortunate spurs. The PLL's are pretty good and necessary for a rubidium since the actual frequency of the rubidium is 6.834,682,612 GHz, which doesn't divide down to anything. They do have good oscillators and the dds will provide up to 20 MHz in the FE-5680A but they are not as good as the crystal oscillator would be. However the crystal oscillators are pretty much always 10 MHz ovenized oscillators in the precision stuff.

A generic oscillator (the $3.00 type) will have pretty minimal specs: http://www.vectron.com/products/vcxo/DatasheetVVA.pdf Where the more expensive (way more) will have a more complete spec http://www.vectron.com/products/vcxo/VX-501-Dual.pdf mostly proving you get what you pay for. Notice the complete phase noise and jitter spec in the more expensive oscillator, including the frequency range for the jitter spec.
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