Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

[vzs]

Originally Posted by bigpandahk

I found this circuit board but there's no information on the "OverKill Audio" Website. Quite similar to yours idea, very simple circuit but without any impedance matching resistor at the in/output. The components are very cheap, will give it a try.

That's similar to the 3. bus-switch idea - but we agreed that either two buffers or RF 50ohm impedance relays would be a better choice.
Regarding the PCB from that pdf... I'm not an experienced PCB designer but that looks quite messy to me: lot of vias, ground-grid nowhere, input connectors pin allocation crappy, only two decoupling caps (no ferrite bead + large decoupling cap). It might not be important but the propagation delays of the chosen ICs are highly different... All in all better nothing then that, sorry.

[vzs]

Originally Posted by qusp

50R to ground just before the input, provided theres no other termination beforehand. check the potato datasheet, I would think this application would be covered, or just steal a scheme from Ti. as I thought, the datasheet test circuit for PO74G125A includes 50ohms to ground after the pulse generator directly before the input, I presume the same applies here.

i'm not the expert in this area, Ian got an opinion? .

I did my homework and found plenty of information (TI's and NXP's App notes are very detailed).
A simple parallel 50ohm resistor would be probably overkill for the source as for 3.3V it would have to source 66mA (quite a lot) so a well dimensioned Thevenin termination might be the answer.

I see that Ian has added source terminations so for short, impedance controlled lines end terminations might not be needed.
Other opinions? thanks!

[qusp]

oh for sure, if you are on the ball with impedance controlled layout and you are using impedance controlled cabling it should be ok it depends on how you define short and how you define controlled =) thevenin would work also, how are you going to choose the values? do you own a suitable scope?

everything on my boards is using 22-47ohms in such positions, but there is also the question of AC termination in the form of a cap after the parallel resistor (~100-150pf), which would lower the current consumption as well

[vzs]

The selection for split termination is controlled by some constraints: the parallel combination of R1 and R2 must equal Zout and IOH, IOL must not be exceeded. Doesn't feels like rocket science. Btw. I can have access to a scope but don't own one.

Are you suing a series-RC parallel termination?

I have neither the experience nor the instruments to do impedance controlled routing and after reading some of Altium's app notes on this and some high speed PCB guidelines I have the feeling that I'm far to design a fair DAC PCB but I will try. So for now I'm satisfied with using those nice u-fl connectors - cables and maybe some terminations =)

[anaeroben]

Hello,

Ian, thank you for async FIFO versus PLL explanation. You have to pre fill buffer in case source clock is slower than DAC's. how is this pre fill samples length choice : is it fixe or according clocks difference (has you detect source frequency)?

About lines and 50 ohms, if you want to do matched lines source (It's likely because pulse generator source is 50 Ohms on Patato test circuit have a 50 Ohms at input), lines (see Missouri S&T index), cables and terminations have to be 50 ohms. also splitter have to be used, it could be make using 3 16 Ohms resistor (Resistive splitter / divider combiner :: Radio-Electronics.Com). but it's likely, there is no 50 ohms lines in fifo board. isn't it ?

have nice week end

[emuman100]

Is there a cost for this project? It's a long thread. Is this an open project or is it not for sale?

[zinsula]

Hi, look here.

[marce]

The resistive spliters are for RF not high speed digital, RF layout techniques are different that HS Digial
Here are a few links regarding various aspects of PCB design in the attached text file. Stuff by Howard Johnson and Eric Bogatin, to name two, is worth looking for for signal integrity and Henry Ott for EMC (which also affects signal integrity).
In my view if you want to do the ultimate design, then you need to look at every aspect of the system, and one of the more critical ones will be the PCB layout. The PCB design shown in #629 is a good example of how NOT to do it.

[qusp]

I wouldnt touch that pcb, the layouts in my build are pretty well handled, i'm not really familiar with thevenin but seemed fair enough when I looked it up as was mentioned in the same breath as series and parallel/parallel+AC termination in the app note I hit for a clock buffer. totally agree about the whole system, cant always control everything, the fifo is great with that as it decouples you from much of what happens beforehand. doesnt mean you throw the handbook out the window but does mean you have some peace of mind.

thanks for the quality references as always marce

[vzs]

Originally Posted by marce

...Here are a few links regarding various aspects of PCB design in the attached text file. Stuff by Howard Johnson and Eric Bogatin, to name two, is worth looking for for signal integrity and Henry Ott for EMC (which also affects signal integrity)...

The attached text file does not show up. Can you please mail it to me to: zsolt_vadaszi at yahoo dot com

I reviewed from Howard Johnson and Martin Graham: High-Speed Digital Design - A handbook of black magic and found it very detailed and understandable with lot of examples.
Thanks.