Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

[NicMac]

Battery management PCB testing group list:

1. qusp
2. bigpandahk
3. SPWONG
4. NicMac
5.
6.
7.
8.
9.
10.

Thanks.

 

[coolhead]

Battery management PCB testing group list:

1. qusp
2. bigpandahk
3. SPWONG
4. NicMac
5. Coolhead
6.
7.
8.
9.
10.

Thanks.

 

[cracra]

Battery management PCB testing group list:

1. qusp
2. bigpandahk
3. SPWONG
4. NicMac
5. Coolhead
6. Cracra
7.
8.
9.
10.

Thanks.

 

[ryanj]

1. qusp
2. bigpandahk
3. SPWONG
4. NicMac
5. Coolhead
6. Cracra
7. ryanj
8.
9.
10.

 

[ryanj]

Ian,

You are an exception to none, one of the most valuable members of the DIY community.

Thank you!

 

[TheShaman]

1. qusp
2. bigpandahk
3. SPWONG
4. NicMac
5. Coolhead
6. Cracra
7. ryanj
8. TheShaman
9.
10.


Thanks Ian!

 

[MisterRogers]

1. qusp
2. bigpandahk
3. SPWONG
4. NicMac
5. Coolhead
6. Cracra
7. ryanj
8. TheShaman
9. Misterrogers
10.


Thanks Ian!
__________________

 

[analog_sa]

So, how bad are the supplied clocks?

Finally put together a test bed: a modified exaU2I via I2S FIFO to Buf 3. As the EXA already has a FIFO and i feed its onboard clocks from a separate regulator, it is not a likely candidate to benefit from the FIFO board.

Still, the reduction in quality with the additional FIFO board in the picture is obvious. My setup is far from ideal - both inputs and outputs to the FIFO board pass through the 7-pin connectors and there obviously is some additional wiring; atm i am using the supplied clocks on the DualXO board and they do not get a dedicated power supply but rather use the 5v output from the FIFO board.

I realise all of these contribute to the audible deficiencies but before switching to mini bnc and sorting out a dedicated regulator for the clocks i would like to ask the obvious: are the supplied clocks just too poor to even bother listening through them? Should i order Crysteks, or wait for the Si570 or try something else?

 

[hochopeper]

I realise all of these contribute to the audible deficiencies but before switching to mini bnc and sorting out a dedicated regulator for the clocks i would like to ask the obvious: are the supplied clocks just too poor to even bother listening through them? Should i order Crysteks, or wait for the Si570 or try something else?

Interesting test setup!


IMO, yes, the supplied clocks are not for listening, just to check that it is operational. The CCHD957 would be my choice. ATM the Si570 is a mere pipedream that may become available in the future if we find another ~30+ people interested.

Are you connecting as sync or async to the BIII?

I would change the clocks before changing the PSU to the dualXO board. Actually Ian this is a question I had been thinking about a little, how much benefit is there likely to be by simply supplying a separate low noise 5V reg (in my case probably sjostrom super reg) to the clock board? I understand that we need to remove L11 before connecting this reg. My problem becomes more complicated because I only have one transformer so all supplies are still coupled there.

 

[analog_sa]

Async atm. Thanks for the advice, will order the Crysteks

 

[ed linssen]

1. qusp
2. bigpandahk
3. SPWONG
4. NicMac
5. Coolhead
6. Cracra
7. ryanj
8. TheShaman
9. Misterrogers
10.ed linssen

 

[syklab]

Si570 interest list:

1. bigpandahk
2. tagheuer
3. hochopeper
4. qusp (of course)
5. AR2 - definitely!
6. wktk_smile
7. hirez69
8. CeeVee - you bet!
9. number9
10. analog_sa - GB maniac
11. edbk
12. atom6422
13. misterrogers - Of Course!
14. NicMac - as usual!
15. Zoran
16. PET-240
17. Coolhead
18. Slartibartfasst
19. SYklab

 

[Regland]

Si570 interest list:

1. bigpandahk
2. tagheuer
3. hochopeper
4. qusp (of course)
5. AR2 - definitely!
6. wktk_smile
7. hirez69
8. CeeVee - you bet!
9. number9
10. analog_sa - GB maniac
11. edbk
12. atom6422
13. misterrogers - Of Course!
14. NicMac - as usual!
15. Zoran
16. PET-240
17. Coolhead
18. Slartibartfasst
19. SYklab
20. Regland

 

[glt]

Finally put together a test bed: a modified exaU2I via I2S FIFO to Buf 3. As the EXA already has a FIFO and i feed its onboard clocks from a separate regulator, it is not a likely candidate to benefit from the FIFO board.

...

Could you show a picture of your FIFO implementation?
Thanks.

 

[qusp]

I would be very surprised if EXA approached the levels of jitter possible with fifo, the clocks do not directly feed the output MCLK with EXA afaik, at least last time I looked (some time ago now) it didnt

confirmed, it still doesnt, the clock clocks the FPGA, which outputs the i2s through the GMRs, so thats 2 layers of additive jitter after the clock, pretty different situation to what we have here

 

[neb001]

Si570 interest list:

1. bigpandahk
2. tagheuer
3. hochopeper
4. qusp (of course)
5. AR2 - definitely!
6. wktk_smile
7. hirez69
8. CeeVee - you bet!
9. number9
10. analog_sa - GB maniac
11. edbk
12. atom6422
13. misterrogers - Of Course!
14. NicMac - as usual!
15. Zoran
16. PET-240
17. Coolhead
18. Slartibartfasst
19. SYklab
20. Regland
21. Neb001

 

[analog_sa]

I would be very surprised if EXA approached the levels of jitter possible with fifo,

Agreed, it's the reason i asked about the clocks. Have you been able to compare the supplied clocks to the Crystek. Is the audible difference dramatic?

 

[glt]

Here is a suggestion for the production Si570 board:

There has been some discussion of using a phase inverted master clock with the Sabre DAC. The Si570 has a Clk+ and Clk- output. One idea is to have both outputs for manual switching.

I don't know how this would make any improvements but it is a positive tweak that has been discussed.

 

[iancanada]

Here is a suggestion for the production Si570 board:

There has been some discussion of using a phase inverted master clock with the Sabre DAC. The Si570 has a Clk+ and Clk- output. One idea is to have both outputs for manual switching.

I don't know how this would make any improvements but it is a positive tweak that has been discussed.

Hi glt,

I use Potato logic FFs on the 570 clock board. The Tpd=2ns. So, all of the I2S signals will be delayed 2ns after raising edge of MCLK. If feed reversed MCLK into ESS9018, take 98.xxx Mhz, the I2S delay will be 5.1+2=7.2ns, that's the only difference. Using slower HC FFs will get the same thing.

Is there any details about reversing 9018 MCLK?

Nice weekend.

Ian

 

[SPWONG]

Si570 interest list:

1. bigpandahk
2. tagheuer
3. hochopeper
4. qusp (of course)
5. AR2 - definitely!
6. wktk_smile
7. hirez69
8. CeeVee - you bet!
9. number9
10. analog_sa - GB maniac
11. edbk
12. atom6422
13. misterrogers - Of Course!
14. NicMac - as usual!
15. Zoran
16. PET-240
17. Coolhead
18. Slartibartfasst
19. SYklab
20. Regland
21. Neb001
22. SPWONG