Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 6 - diyAudio
Go Back   Home > Forums > Source & Line > Digital Line Level

Digital Line Level DACs, Digital Crossovers, Equalizers, etc.

Please consider donating to help us continue to serve you.

Ads on/off / Custom Title / More PMs / More album space / Advanced printing & mass image saving
Reply
 
Thread Tools Search this Thread
Old 10th August 2011, 02:09 AM   #51
diyAudio Member
 
iancanada's Avatar
 
Join Date: Dec 2009
Location: Toronto
Default Feeling the jitter, my terrible experience

After got this I2S FIFO working, the first thing I couldn’t help to do was experiencing the ‘known’ jitter, although finally it approved the feeling was very bad. So at here, I just don’t suggest doing this kind of meaningless job anymore.

People did a lot of research about how the jitter should sound like and we could also find out the simulation results, the equations, and the spectrum plots from websites connected to this issue. So roughly I know how it would be.

I just came across having an IDT 5V9885 clock generator board for my previous FPGA projects. This clock board is not suitable for digital audio application because it comes with 200ps peak-to-peak period jitter; it was developed originally for FPGA design verification because it has three internal programmable PLLs. The only reason I want to use it was because on chip it integrated a programmable spread spectrum generation function, which means I could generate the ‘know’ jitter by programming the SSC.

The first step I did was programming the 5V9885 to generate an 11.2986MHz clock without SSC from CLK2 and connected it into my system by replacing the clock board I had before. Again, I use battery power this 5V9885 board to exclude the influence of the power supply. It sounds OK, same level as the analog output quality of a hundred bucks DVD player and worse than the direct I2S and MCLK output from DIR9001.

And then, I programmed the SSC to generate the same frequency clock but with +-200ps period jitter with 2KHz modulation. When I turned it on, I was totally shocked. The sound was so bad; I never thought my B&W 804 speakers could sound horrible like that. Everything was mixed up at background and I couldn’t distinguish the positions of the singer and the instruments. It was noisy and without any details. I lost the focus, lost the depth, lost the 3D feelings. After a while, I got a bit sick and my ears were very uncomfortable. So I stopped this research which I thought I could go deeper. When I switched it back to DIR9001, I found it still sound bad. I started to suspect something wrong with my system. But finally I realize it was something wrong with my listening and it didn’t recover until hours later.

That terrible experience was almost killing my motivation to continue my hobby of audio DIY and making I feel bad, so I decided not to do this kind of evaluation any more. Although my jitter experiencing testing is not a typical case and that kind of jitter may not exist in the real world of digital audio, but at least it confirmed what they said about how the jitter should sounds like was true.

I think I really need doing something nice to make me feel better, for example, finding out the beauty from clocksJ.
Attached Images
File Type: jpg ClockGenerator5V9885.JPG (485.4 KB, 2098 views)
File Type: jpg 5V9885Setting.JPG (61.4 KB, 2002 views)
  Reply With Quote
Old 10th August 2011, 08:10 AM   #52
qusp is offline qusp  Australia
diyAudio Member
 
qusp's Avatar
 
Join Date: Oct 2009
Location: Brisbane, Australia
thats a cool story and yes i think i have experienced a similar situation on occasion. basically it removes any specificity to the imaging, which on headphones is quite disorienting. thats a very interesting looking board, can you tell me more?
  Reply With Quote
Old 12th August 2011, 12:32 AM   #53
diyAudio Member
 
iancanada's Avatar
 
Join Date: Dec 2009
Location: Toronto
Quote:
Originally Posted by qusp View Post
thats a cool story and yes i think i have experienced a similar situation on occasion. basically it removes any specificity to the imaging, which on headphones is quite disorienting. thats a very interesting looking board, can you tell me more?
Hi Qusp, That clock board was just an IDT 5V9885 EVB, nothing special. You can download all the docs and softwares from IDT - Integrated Device Technology - EEPROM Reprogrammable > 5V9885C . 5V9885 is not a most updated programmable clock generator. But the good thing is you can generate any frequency you want. That is a very usefull feature for testing the boards. For example, your can generate the master clock for different Fs and get your board go through all the case. We can find something even better from TI or AD now.

I still can't come back to the job of coding and testing the FIFO clock board which was almost finished. Hopefully I could show you something on the weekend. Ian

Last edited by iancanada; 12th August 2011 at 12:52 AM.
  Reply With Quote
Old 14th August 2011, 01:19 AM   #54
diyAudio Member
 
iancanada's Avatar
 
Join Date: Dec 2009
Location: Toronto
Hi guys, I’m coming back.

I just could be able to show you the first clock board I designed for this FIFO project: the Double XO Clock Board. Please see the attached pictures.
The features are as below:

1. Frequency supported
44.1KHz 16bit (24bit/32bit ready)
48KHz 16bit (24bit/32bit ready)
88.2KHz 16bit/24bit (32bit ready)
96KHz 16bit/24bit (32bit ready)
176.4KHz 16bit/24bit/32bit
192KHz 16bit/24bit/32bit

2. Switching the MCLK and *Fs automatically according to the input I2S stream;

3. XO options for the socket U1:
11.2896MHz (go 44.1K and 88.2K)
Or, 22.5792MHz (go 44.1K, 88.2K and 176.4K)
14Pin or 9Pin standard XO with 3.3V Vcc

XO options for the socket U2:
12.2880MHz (go 48K and 96K)
Or, 24.5760MHz (go 48K, 96K and 192K)
14Pin or 9Pin standard XO with 3.3V Vcc

4. Re-clock function was equipped on board;

5. Manual frequency switching button for optional standalone working mode;

6. Output the MCLK and I2S signals directly without passing through FIFO;

7. Implement a relay for frequency switching to avoid any additive jitter from buffering the MCLK;

8. Frequency settings will be saved and applied automatically at next power up.

The FIFO board was designed having an optional frame connected which is compatible with the frame on the clock board(this idea just make the FIFO board could be easily integrated with different clock solution). We can pick up the clock board from its original frame by a side cutter, and hook it up to the FIFO board by four rubber rings to make them linked together as a whole piece; or, we could cut the frame from the FIFO board and make the FIFO and the clock board located separately. It’s quite flexible at this point. The purpose of using those rubber rings is to reduce the mechanical vibration which could also introduce the jitter into the XO output.

Interface with the FIFO board, basically only a 10 pin FFC cable is needed. If we want to use the re-clock function on the clock board, an additional I2S bridge cable will be connected. That’s all, nothing else, very easy.

This double XO clock board has a frequency management MCU. During normal operation, this MCU will run at deep sleep mode, or power down mode. In this mode, all of the clocks, include CPU clock, IO clock and watchdog clock, are stopped. That means the MCU do not generate any EMI noise at this time. When the frequency detecting logic on the FIFO board found input I2S frequency was changed, it will wake up the MCU by pulling down the interrupt line, and at same time silence the I2S output. After the wakeup, the MCU will set a new MCLK frequency as well as the *Fs according to the information provided by the FIFO board. Once the new frequency was set and confirmed good, the MCU will back to the deep sleep mode again.

There are nine LEDs on this clock board. Six of them are Fs frequency indicator to indicate six working Fs frequency (form 44.1 KHz to 192 KHz); Three of them are the *Fs indicator to indicate 128,256 or 512 *Fs.

This clock board, together with the FIFO board, are working very well with my system. The frequency switching function was amazing. For example, I’m playing a 44.1K APE by the foobar2000 player, and then I open a 96 KHz 24 bit APE file. The lock LED on the FIFO board will start flashing and the empty LED will turn on, after a while(around 2 seconds), I can hear a little click from the relay, and then the lock LED go solid, empty led turned off, the LEDs on the clock board new indicate 96Khz and 256Fs, and then the music starts. Very cool.

Again, both of the FIFO board and the clock board do not influence the sound quality (of cause they are bit perfect), what really decide the sound quality are the XOs which the clock board is equipped with. So, next step, the most important thing for me is looking for better clocks.

Enjoy the pictures. Ian
Attached Images
File Type: jpg DoubleXOclockBoard1.JPG (674.5 KB, 1924 views)
File Type: jpg DoubleXOclockBoard2.JPG (648.6 KB, 1717 views)
File Type: jpg FIFOframe.JPG (559.6 KB, 1628 views)
File Type: jpg WorkWithFIFOboard.JPG (679.0 KB, 767 views)
File Type: jpg XOsockets.JPG (573.3 KB, 746 views)
File Type: jpg ReclockSection.JPG (573.5 KB, 641 views)
File Type: jpg FrequencyIndicatorLEDs.JPG (461.9 KB, 679 views)

Last edited by iancanada; 14th August 2011 at 01:45 AM.
  Reply With Quote
Old 14th August 2011, 03:40 AM   #55
Bunpei is offline Bunpei  Japan
diyAudio Member
 
Join Date: Aug 2008
Quote:
Originally Posted by iancanada View Post
So, next step, the most important thing for me is looking for better clocks.
I'd like to recommend;
CMOS output Crystal Clock Oscillator NZ2520SD
manufactured by a Japanese leading crystal maker, Nihon Dempa Kogyo Co., Ltd.;
NZ2520SD(OA / AV)/Crystal Clock Oscillators/NDK
http://www.ndk.com/images/products/c...NSA3449E_e.pdf

The model has a remarkable low phase noise profile. According to their measurement result sheet, Phase Noise [dBc/Hz] 26MHz 3.3V for 5 samples
1Hz: max -76, min -81
10Hz: max -108, min -111
100Hz: max -136, min -138
1kHz: max -151, min -152
10kHz: max -156, min -157

The component is also available for personal users by way of a Japanese online web store, chip1stop.
Chip One Stop - Shopping Site for Electronic Components and Semiconductors

The price I bought was 1,500 JPY / piece ( 20 USD/ piece )
and 1,000 JPY/10 pieces.
  Reply With Quote
Old 15th August 2011, 06:08 PM   #56
diyAudio Member
 
iancanada's Avatar
 
Join Date: Dec 2009
Location: Toronto
Quote:
Originally Posted by Bunpei View Post
I'd like to recommend;
CMOS output Crystal Clock Oscillator NZ2520SD
manufactured by a Japanese leading crystal maker, Nihon Dempa Kogyo Co., Ltd.;
Thanks Bunpei. Thank you so much for those recommendations.

Very good XO with impressed phase noise performance, especially at the low range.
I'm gonna register a membership at that website and try to get the quotation. It seems both of 22.5792MHz and 24.5760Mhz, they don't keep in stock currentlly.
The only thing I'm concerned about is .. if it is available delivery to Canada.
I'll come back to you if I have more questions. Thanks again. Have a nice week. Ian
  Reply With Quote
Old 15th August 2011, 10:06 PM   #57
diyAudio Member
 
Join Date: Oct 2003
Location: Central Oregon
I designed a similar product several years ago, the Pace-Car. The difference is that the Pace-Car works in two synchronous modes and one asynchronous mode and does not overrun/underrun the FIFO. The one you designed is a lot like the Genesis Digital Lens, which had large enough FIFO to last through most CDs without under/overrun. The clock was old on the lens, so the jitter was not competitive with modern clocks. I thought about doing this initially, but with long playlists and computer audio becoming the favored method of playback, the over/underrun was inevitable.

You are definitely correct, that the clock is the most important part of this design, as all digital audio designs. In the past, I have sold upgrade clock options for all of my products using either Superclock4 or Ultraclock from Audiocominternational. The Ultraclock is the best sounding clock IMO, and that's probably why it commands $800 from Reference Audio Mods, the distributor. I charged the same when I offered it. I now have my own clock design, so I have discontinued use of Superclock4 and Ultraclock. The good news for you is that I still have some Ultraclocks in stock. I am willing to sell 2 Ultraclocks in any frequency you want for $700.00. These start with a fundamental crystal (not overtone) generating a sine-wave and then a fast comparator and buffer for the TTL output. I can confingure them for 5V or 3.3V output and any output impedance from 10 ohms to 110 ohms.

I have evaluated a lot of clocks over the last 12 years, and I can tell you that the only ones besides the Audiocom offerings that are interesting are expensive custom clocks which must be ordered in large quantities, usually 50 or 100 in each frequency, and they take some time to get. A minimum $1000 investment. Even once you get these, they must be powered with an excellent discrete regulator design to actually achieve low jitter. There are no guarantees that your design will deliver the specsheet jitter numbers.

This is why the Ultraclock is a nice alternative. It runs on 12VDC and has decent on-board op-amp based regulators and it just sounds good. Any frequency you need. Battery power to the 12VDC is even better.

if interested contact me at nugent@empiricalaudio.com

Steve N.
Empirical Audio
__________________
The very best in computer audio

Last edited by audioengr; 15th August 2011 at 10:14 PM.
  Reply With Quote
Old 17th August 2011, 01:55 AM   #58
diyAudio Member
 
Join Date: Jan 2006
Location: California
Quote:
Originally Posted by iancanada View Post
Hi guys, I’m coming back.

Enjoy the pictures. Ian
It looks like you took great effort to design the clock board. I do have a few comments:
1) The clock switching based on input signal sample rate change should be instantaneous. Other than the time waiting for the incoming signal to be stable (to verify the sample rate change), there should be no need to wait for 2 seconds. Clearing the FIFO? The old data should be discarded anyway.
2) The CPLD should be able to generate all the control signals used to switch the oscillators. Having an MCU is nice but I don't see the necessity.
3) Using a relay to switch between clocks may not be a good idea. For starters, it is not glitch-free. That's probably why you use a separate controller because you need to reset the CPLD after the clock switching. Second, the regular relay is not suitable for clock switching. You would need the ones rated for GHz signals just to get the impedance control right - and they are not cheap.
  Reply With Quote
Old 17th August 2011, 11:17 PM   #59
diyAudio Member
 
iancanada's Avatar
 
Join Date: Dec 2009
Location: Toronto
Quote:
Originally Posted by audioengr View Post
I designed a similar product several years ago, the Pace-Car.
Hi Steve,

Thank you so much for sharing your design experience. I took a look at your website. You did some innovative products, very impressed. It seems we achieve the similar target by different direction. I roughly understand your method, very smart idea, I like it.
My solution is more direct, just a standard big enough FIFO with I2S interface. I noticed the ‘under/over run’ issue, so I developed a smart FIFO logic inside the FPGA, in most of the cases, it does not ‘under/over run’ neither, even having a long playlist from a computer based player.
Totally agree with you on the point of power supply. Yes, I found the clock circuit is very sensitive to the EMI noise introduced by the power supply.
My project is still undergoing and I’m gonna try different clock solutions later on. Thank you so much for the offer, just hope I could have chance try your famous Ultraclock meanwhile. I’ll take into consideration. Regards. Ian
  Reply With Quote
Old 19th August 2011, 03:13 AM   #60
diyAudio Member
 
iancanada's Avatar
 
Join Date: Dec 2009
Location: Toronto
Quote:
Originally Posted by simmconn View Post
1) The clock switching based on input signal sample rate change should be instantaneous. Other than the time waiting for the incoming signal to be stable (to verify the sample rate change), there should be no need to wait for 2 seconds. Clearing the FIFO? The old data should be discarded anyway.
2) The CPLD should be able to generate all the control signals used to switch the oscillators. Having an MCU is nice but I don't see the necessity.
3) Using a relay to switch between clocks may not be a good idea. For starters, it is not glitch-free. That's probably why you use a separate controller because you need to reset the CPLD after the clock switching. Second, the regular relay is not suitable for clock switching. You would need the ones rated for GHz signals just to get the impedance control right - and they are not cheap.
Hi Simmconn, Thank you so much for those comments. Appreciate. But at some of points, I’m afraid I couldn’t 100% agree with you. I think it was mainly because we keep the different idea on the I2S FIFO project design. I’d like to discuss with you.

If you took a close look at the pictures, you may find out, at the clock section, I have different design idea. My design idea on the clock board is kind of open concept. My FIFO board could not only compatible with the different XOs on this double XO clock board, but also expend different clock/timing solutions come together with different clock boards, such as PLL, DDS, synthesizer and other technologies. To achieve this function, I need set up a protocol between the FIFO and the clock board. According to same protocol, the MCU on different clock boards could perform the solution independent frequency management. That means, if I have a new clock technology five years later, I still could design a clock board at that time and make it working very well with today’s FIFO platform, because the protocol keeps no change. This advantage will show obviously on my subsequence clock board design. Comparing with the benefit it brought, that MCU is worth it. To keeping bring the ‘fun’, I’ll design series of clock boards, this is only the first one.

On the other hand, my I2S FIFO is working at slave mode; the clock board is the master device with highest priority. All of signals are generated by the clock board at finial stage in order to get the better jitter performance. I don’t think using a slave device to dominate the master frequency control is a good idea. Sorry, at this point, I couldn’t agree with you.

Talking about the relay, I couldn’t find anything more suitable for this double XO configuration other than it, unless you power and run the two XOs at same time which is the way I don’t like. Comparing with FPGA and other logic switching circuit, to switch between clocks, the relay almost introduces no additive jitter. That was the reason I use it. Yes you are right, some of the relays may not suitable for switching the clock, but not include the one I selected. You may notice the good high frequency performance from the insertion loss plot I attached (below 0.1dB at 20 Mhz, below 0.8dB at 1 GHz). Regarding to the impedance match, of course, the dedicated RF relay comes with better performance. But how much we could gain from it? Just let me figure it out. The RF relay could be considered as a half inch cable which we could hookup the source terminate resistor Rs before, while, the non-RF relay could be considered as a half inch lead which we have to hookup the Rs after. The only difference in between is without or with that half inch of additional lead on the XO output pin. For the MCLK up to 24.5760 Mhz with 1-3ns raising/falling time, I don’t see that half inch will make big difference on the output jitter performance. But anyway, if have chance, I’d like to try the RF relay to confirm this matter.

About the switching time, thank you for the noticing. I may have some idea to make it shorter. The only thing I have to compromise with is the frequencies detection accuracy which may influence the performance of the synthesizer based clock board I might design later on. Fortunately, Fs changing only happen at the moment when people switching the source but not the moment when it was playing.

Just hope you could re-start your project. I believe different idea may suitable for different platform. Ian
Attached Images
File Type: jpg RelayHiFrequency.JPG (61.7 KB, 649 views)

Last edited by iancanada; 19th August 2011 at 03:30 AM.
  Reply With Quote

Reply


Hide this!Advertise here!
Thread Tools Search this Thread
Search this Thread:

Advanced Search

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are Off
Pingbacks are Off
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
XMOS-based Asynchronous USB to I2S interface Lorien Digital Source 2129 28th August 2014 03:59 PM
exaU2I - Multi-Channel Asynchronous USB to I2S Interface exa065 exaDevices 1357 3rd March 2014 08:51 PM
DAC chip selection + I2S jitter questions drwho9437 Digital Line Level 2 26th July 2010 12:50 PM
Simple FIFO to I2S CPLD, for MCU players / reclocking KOON3876 Digital Line Level 21 19th September 2008 04:00 PM
asynchronous reclocking and low jitter clocks ash_dac Digital Source 3 8th February 2005 09:22 AM


New To Site? Need Help?

All times are GMT. The time now is 12:56 PM.


vBulletin Optimisation provided by vB Optimise (Pro) - vBulletin Mods & Addons Copyright © 2014 DragonByte Technologies Ltd.
Copyright ©1999-2014 diyAudio

Content Relevant URLs by vBSEO 3.3.2