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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
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Old 24th May 2012, 04:22 PM   #581
qusp is offline qusp  Australia
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guess I should find out who lead the team for the hd600 and see if I can get it edited in =)
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Old 26th May 2012, 10:55 AM   #582
wktk_smile is offline wktk_smile  Japan
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Hi,

I have tried "double speed mode" with async FIFO + dual XO board (and Buffalo2), using recently purchased 45mhz and 49mhz cchd-957.
modifying was quite easy, except mounting cchd-957 because I didn't have suitable adopter board.


Tested playing 352.8khz music (from 2L trial download) and 384khz test track (from MSB website).
both were played fine with bypassing OSF mode of ES9018.

Great!
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Old 26th May 2012, 09:08 PM   #583
wktk_smile is offline wktk_smile  Japan
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This is my ugly XO adopter board.
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Old 27th May 2012, 05:00 AM   #584
qusp is offline qusp  Australia
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hitech!
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Old 29th May 2012, 01:51 AM   #585
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by bigpandahk View Post
Hi Ian

I need a couple of PCB for my dual clock board, but I can't find any information in the GB.
Will post later

Ian
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Old 29th May 2012, 01:57 AM   #586
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by wktk_smile View Post
Hi,

I have tried "double speed mode" with async FIFO + dual XO board (and Buffalo2), using recently purchased 45mhz and 49mhz cchd-957.
modifying was quite easy, except mounting cchd-957 because I didn't have suitable adopter board.


Tested playing 352.8khz music (from 2L trial download) and 384khz test track (from MSB website).
both were played fine with bypassing OSF mode of ES9018.

Great!
Quote:
Originally Posted by wktk_smile View Post
This is my ugly XO adopter board.
Good to know that. I'll try the 3XXkhz later. Will supply the good XO adapter KIT for sure together with GBII. Your XOs will look nicer.

What the difference between OSF/bypass ?

Ian
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Old 29th May 2012, 06:52 AM   #587
qusp is offline qusp  Australia
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I have tried OSF bypass before too and i'm not quite sure about the results, I believe its one of the ess strengths, the filters seem very well handled despite not being linear phase. I think by running synch AND OSF bypass you are making it just like any other high performance dac
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Old 29th May 2012, 12:45 PM   #588
wktk_smile is offline wktk_smile  Japan
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When playing 352.8k files, I never felt OSF mode is necessary. Hard to decide which is better for me between OSF mode and bypassing OSF mode.

With lower SR recordings, high frequencies are more natural with OSF mode.
Especially when playing 16/44.1k materials I never bypass it.

These are my subjective opinion and might differ with different post filter designs.
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Old 30th May 2012, 02:11 AM   #589
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Default I2S to PCM convertor daughter board PCB design

Hi Vzs, Hi Zinsula

Are you there?

The I2S to PCM convertor daughter board got some progress. The PCB layout alos finished. All dimensions are as same as the clock board and could be stacked together. Please see the attached pictures for details and let me know for your suggestions.

I don't think it could catch up with the GB II. But I hope I can order the prototype PCB together with GB II.

Regards,

Ian
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File Type: jpg I2StoPCMlayout.jpg (138.5 KB, 572 views)
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Old 30th May 2012, 07:06 AM   #590
zinsula is offline zinsula  Switzerland
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Quote:
Originally Posted by iancanada View Post
[...]Are you there?[...]
Yes!

I didn't feel to ask you about that additional board, as you seem to have already enough work right now.

From the picture, not everything is clear to me...
- What is J5 for?
- I assume U5 is a D-FlipFlop, do you reclock all 6 lines with this? As DATA lines should be quiet during conversion, this might be OK, on the other hand, reclocking CLK and LLLR with separate single (and properly decoupled) FlipFlops (picogates) would make sure those lines are less influenced from each other.
-J7, it would be good if you can put DR and DRn, and DL and DLn as pairs. These pairs of data are kind of a balanced signal (complementary) and small loops are beneficial, also helps the layout on the DAC board.
It would be good to have something like this:
GND-CLK-GND-LLLR-GND-DLn-DL-GND-DR-DRn
Those using only DL and DR still would have a GND cable in between. A 10 pin connector would be needed though...
- I assume you did it already with U3 and U4 but not sure: Good deecoupling of U1 and U5. U5 is critical for performance and should get very clean power.

Thank you anyway! Ciao
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