Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 53 - diyAudio
Go Back   Home > Forums > Source & Line > Digital Line Level

Digital Line Level DACs, Digital Crossovers, Equalizers, etc.

Please consider donating to help us continue to serve you.

Ads on/off / Custom Title / More PMs / More album space / Advanced printing & mass image saving
Reply
 
Thread Tools Search this Thread
Old 15th May 2012, 01:54 AM   #521
qusp is offline qusp  Australia
diyAudio Member
 
qusp's Avatar
 
Join Date: Oct 2009
Location: Brisbane, Australia
Quote:
Originally Posted by iancanada View Post
Thanks hochopeper,

Like my Salas shunts ? The temperature goes up to 60 degree C after 2 hours running, is that safe enough?
where was this temperature taken? the es9018 should not be operated at higher than ambient ~70c and should be below. given you are on breadboard I gather you mean the heatsink? how about the current set resistor temp?

Quote:
The best way is solder the u.fl direct to the board as qusp did, but how about those already has the connecter soldered on board ?
solder it under the board of course

Ian, as for the DPLL, as I understand it, its never turned off completely in a 'sync mode', but the closer BCK becomes to in sync with MCK, it has to do less and less work, until it is completely inactive when both come from the same source. so to be really picky about it, you should use the same length cables for i2s and mclk for ess, not just close as in the fifo manual; even if it means the cables must do a small 'loop' back to the inputs

Last edited by qusp; 15th May 2012 at 02:03 AM.
  Reply With Quote
Old 15th May 2012, 02:56 AM   #522
diyAudio Member
 
iancanada's Avatar
 
Join Date: Dec 2009
Location: Toronto
Quote:
Originally Posted by qusp View Post
where was this temperature taken?
solder it under the board of course

Ian, as for the DPLL, as I understand it, its never turned off completely in a 'sync mode', but the closer BCK becomes to in sync with MCK, it has to do less and less work, until it is completely inactive when both come from the same source. so to be really picky about it, you should use the same length cables for i2s and mclk for ess, not just close as in the fifo manual; even if it means the cables must do a small 'loop' back to the inputs
What a smart idea, Yes, solder it under the board!

BTW, the ~70C was measured at the heat sink of the shunt reg .
__________________
Ian GBV - I2S to PCM converter board & FIFO KIT
http://www.diyaudio.com/forums/group...ml#post3662743
  Reply With Quote
Old 15th May 2012, 03:01 AM   #523
diyAudio Member
 
iancanada's Avatar
 
Join Date: Dec 2009
Location: Toronto
Quote:
Originally Posted by glt View Post
use "lowest" Block 1 switches 5, 6, 7: On, OFF, OFF

When I use "lowest" and the source is a FPGA based I2S, I have to wait about one hour for the DAC to warm up; otherwise I get drop-offs (the DPLL looses synch)
Yes, when I set the switch to "lowest", I got drop-offs too. It's sound a littlt bit better for me, but I gave up after half hour 'warm up' .
__________________
Ian GBV - I2S to PCM converter board & FIFO KIT
http://www.diyaudio.com/forums/group...ml#post3662743
  Reply With Quote
Old 15th May 2012, 07:34 AM   #524
Salas is offline Salas  Greece
diyAudio Chief Moderator
 
Salas's Avatar
 
Join Date: Oct 2002
Location: Athens-Greece
Quote:
Originally Posted by iancanada View Post

BTW, the ~70C was measured at the heat sink of the shunt reg .
That 3 regs carrying heatsink temp sounds high enough. When fins are facing down it ain't helping. Better to fix upright for improved convection or even to force cool it through the fins with a low speed silent fan.
Those boards and Mosfets are tough, but for long term reliability the things to keep in check are the core temp in the semis and the temp on the lytics, in any kind of electronics build. The Mosfets in this kind of reg have an RthJC of 6.3C/W. Means for every Watt they burn, their core climbs 6.3C hotter than their shell. Their silicon junction core meltdown point is 150C and its good they stay under a line of 100C long term. By probing their shell with a thermocouple or by aiming it with an IR thermo gun, plus knowing what voltage and current each one runs you can estimate their core temps. Say you measure 50C on a Mosfet case that runs 0.5A at 5V, its core is at 65.75C for example.
Check the temps on the electrolytics too, should not let climb near their rated temp as printed on their sleeves. Rule of thumb, when halving temp you quadruple long term reliability in electronics. Revisit the thermal plan if ever to box it up because then the ambient temp and convection are gonna get tougher issues IMHO. Nice build by the way, nice configuration. Enjoy.
  Reply With Quote
Old 15th May 2012, 01:46 PM   #525
Bunpei is offline Bunpei  Japan
diyAudio Member
 
Join Date: Aug 2008
Quote:
Originally Posted by iancanada View Post
Yes, when I set the switch to "lowest", I got drop-offs too.
May I ask which DPLL Bandwidth parameter is the best notch you obtained for the play of 192kHz/24bit PCM through the I2S signal path employing your FPGA (The minimum DPLL Bandwidth parameter to maintain a stable lock.) ? "Medium Low" or "Low"?
  Reply With Quote
Old 15th May 2012, 11:41 PM   #526
diyAudio Member
 
iancanada's Avatar
 
Join Date: Dec 2009
Location: Toronto
Quote:
Originally Posted by Salas View Post
That 3 regs carrying heatsink temp sounds high enough. When fins are facing down it ain't helping. Better to fix upright for improved convection or even to force cool it through the fins with a low speed silent fan.
Those boards and Mosfets are tough, but for long term reliability the things to keep in check are the core temp in the semis and the temp on the lytics, in any kind of electronics build. The Mosfets in this kind of reg have an RthJC of 6.3C/W. Means for every Watt they burn, their core climbs 6.3C hotter than their shell. Their silicon junction core meltdown point is 150C and its good they stay under a line of 100C long term. By probing their shell with a thermocouple or by aiming it with an IR thermo gun, plus knowing what voltage and current each one runs you can estimate their core temps. Say you measure 50C on a Mosfet case that runs 0.5A at 5V, its core is at 65.75C for example.
Check the temps on the electrolytics too, should not let climb near their rated temp as printed on their sleeves. Rule of thumb, when halving temp you quadruple long term reliability in electronics. Revisit the thermal plan if ever to box it up because then the ambient temp and convection are gonna get tougher issues IMHO. Nice build by the way, nice configuration. Enjoy.
Thanks Salas,

It seems I need add more heatsink to lower the temp. Yes, you are right, the fins facing down no good for radiating the heat but I have no choice .
Or, maybe, open a window underneath.

BTW, I like your regs, very thoughtful design with good performance. I bought three sets from the GB .

Regards,

Ian
__________________
Ian GBV - I2S to PCM converter board & FIFO KIT
http://www.diyaudio.com/forums/group...ml#post3662743
  Reply With Quote
Old 16th May 2012, 12:48 AM   #527
Salas is offline Salas  Greece
diyAudio Chief Moderator
 
Salas's Avatar
 
Join Date: Oct 2002
Location: Athens-Greece
The hot air has to rise vertical to the fins as it tends moving up so to efficiently convect heat from their surface. Better bolt it on a metal slab to increase the thermal absorbing mass than to make a down facing window. Nice that you liked them. Thanks.
  Reply With Quote
Old 16th May 2012, 12:49 AM   #528
diyAudio Member
 
iancanada's Avatar
 
Join Date: Dec 2009
Location: Toronto
Quote:
Originally Posted by Bunpei View Post
May I ask which DPLL Bandwidth parameter is the best notch you obtained for the play of 192kHz/24bit PCM through the I2S signal path employing your FPGA (The minimum DPLL Bandwidth parameter to maintain a stable lock.) ? "Medium Low" or "Low"?
Hi Bunpei,

I have to set bandwidth to 'low-middle' to achieve long term stable lock with 192Khz I2S.

Ian
__________________
Ian GBV - I2S to PCM converter board & FIFO KIT
http://www.diyaudio.com/forums/group...ml#post3662743
  Reply With Quote
Old 16th May 2012, 03:36 AM   #529
diyAudio Member
 
Join Date: Jul 2009
Quote:
Originally Posted by iancanada View Post
I just got time this weekend playing with my ESS9018 DAC.
My system:
B&W 804, Pass A5, Pass 1.7, Buffalo III, LegatoIV,SalasShuntReg...
Hi Ian

I am also planning to use the SalasShuntReg to power the BIII. Just want to confirm my understanding is correct, you use 3 SSRLV to power the 3 trident and each set at 5.25V 100mA output? With such small current, why it generate so many heat (60 deg)???
  Reply With Quote
Old 16th May 2012, 04:04 AM   #530
diyAudio Member
 
Join Date: Feb 2009
Location: Brisbane, Australia
Quote:
Originally Posted by bigpandahk View Post
Hi Ian

I am also planning to use the SalasShuntReg to power the BIII. Just want to confirm my understanding is correct, you use 3 SSRLV to power the 3 trident and each set at 5.25V 100mA output? With such small current, why it generate so many heat (60 deg)???
I think he's actually running +/- ssrlv to power the legato and a single +ve salas shunt to the VD terminals on the BIII which then feeds all 3 tridents. That was why I got confused when I first only saw 2 shunt regs (didn't spot the one hiding on the side) because powering BIII from the same supply as +ve rail to the legato would be a bit ......

Last edited by hochopeper; 16th May 2012 at 04:10 AM.
  Reply With Quote

Reply


Hide this!Advertise here!
Thread Tools Search this Thread
Search this Thread:

Advanced Search

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are Off
Pingbacks are Off
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
XMOS-based Asynchronous USB to I2S interface Lorien Digital Source 2167 25th September 2014 08:58 PM
exaU2I - Multi-Channel Asynchronous USB to I2S Interface exa065 exaDevices 1357 3rd March 2014 08:51 PM
DAC chip selection + I2S jitter questions drwho9437 Digital Line Level 2 26th July 2010 12:50 PM
Simple FIFO to I2S CPLD, for MCU players / reclocking KOON3876 Digital Line Level 21 19th September 2008 04:00 PM
asynchronous reclocking and low jitter clocks ash_dac Digital Source 3 8th February 2005 09:22 AM


New To Site? Need Help?

All times are GMT. The time now is 09:25 AM.


vBulletin Optimisation provided by vB Optimise (Pro) - vBulletin Mods & Addons Copyright © 2014 DragonByte Technologies Ltd.
Copyright 1999-2014 diyAudio

Content Relevant URLs by vBSEO 3.3.2