Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

[qusp]

Originally Posted by iancanada

Thanks hochopeper,

Like my Salas shunts ? The temperature goes up to 60 degree C after 2 hours running, is that safe enough?

where was this temperature taken? the es9018 should not be operated at higher than ambient ~70c and should be below. given you are on breadboard I gather you mean the heatsink? how about the current set resistor temp?

The best way is solder the u.fl direct to the board as qusp did, but how about those already has the connecter soldered on board ?

solder it under the board of course

Ian, as for the DPLL, as I understand it, its never turned off completely in a 'sync mode', but the closer BCK becomes to in sync with MCK, it has to do less and less work, until it is completely inactive when both come from the same source. so to be really picky about it, you should use the same length cables for i2s and mclk for ess, not just close as in the fifo manual; even if it means the cables must do a small 'loop' back to the inputs

[iancanada]

Originally Posted by qusp

where was this temperature taken?
solder it under the board of course

Ian, as for the DPLL, as I understand it, its never turned off completely in a 'sync mode', but the closer BCK becomes to in sync with MCK, it has to do less and less work, until it is completely inactive when both come from the same source. so to be really picky about it, you should use the same length cables for i2s and mclk for ess, not just close as in the fifo manual; even if it means the cables must do a small 'loop' back to the inputs

What a smart idea, Yes, solder it under the board!

BTW, the ~70C was measured at the heat sink of the shunt reg .

[iancanada]

Originally Posted by glt

use "lowest" Block 1 switches 5, 6, 7: On, OFF, OFF

When I use "lowest" and the source is a FPGA based I2S, I have to wait about one hour for the DAC to warm up; otherwise I get drop-offs (the DPLL looses synch)

Yes, when I set the switch to "lowest", I got drop-offs too. It's sound a littlt bit better for me, but I gave up after half hour 'warm up' .

[Salas]

Originally Posted by iancanada

BTW, the ~70C was measured at the heat sink of the shunt reg .

That 3 regs carrying heatsink temp sounds high enough. When fins are facing down it ain't helping. Better to fix upright for improved convection or even to force cool it through the fins with a low speed silent fan.
Those boards and Mosfets are tough, but for long term reliability the things to keep in check are the core temp in the semis and the temp on the lytics, in any kind of electronics build. The Mosfets in this kind of reg have an RthJC of 6.3C/W. Means for every Watt they burn, their core climbs 6.3C hotter than their shell. Their silicon junction core meltdown point is 150C and its good they stay under a line of 100C long term. By probing their shell with a thermocouple or by aiming it with an IR thermo gun, plus knowing what voltage and current each one runs you can estimate their core temps. Say you measure 50C on a Mosfet case that runs 0.5A at 5V, its core is at 65.75C for example.
Check the temps on the electrolytics too, should not let climb near their rated temp as printed on their sleeves. Rule of thumb, when halving temp you quadruple long term reliability in electronics. Revisit the thermal plan if ever to box it up because then the ambient temp and convection are gonna get tougher issues IMHO. Nice build by the way, nice configuration. Enjoy.

[Bunpei]

Originally Posted by iancanada

Yes, when I set the switch to "lowest", I got drop-offs too.

May I ask which DPLL Bandwidth parameter is the best notch you obtained for the play of 192kHz/24bit PCM through the I2S signal path employing your FPGA (The minimum DPLL Bandwidth parameter to maintain a stable lock.) ? "Medium Low" or "Low"?

[iancanada]

Originally Posted by Salas

That 3 regs carrying heatsink temp sounds high enough. When fins are facing down it ain't helping. Better to fix upright for improved convection or even to force cool it through the fins with a low speed silent fan.
Those boards and Mosfets are tough, but for long term reliability the things to keep in check are the core temp in the semis and the temp on the lytics, in any kind of electronics build. The Mosfets in this kind of reg have an RthJC of 6.3C/W. Means for every Watt they burn, their core climbs 6.3C hotter than their shell. Their silicon junction core meltdown point is 150C and its good they stay under a line of 100C long term. By probing their shell with a thermocouple or by aiming it with an IR thermo gun, plus knowing what voltage and current each one runs you can estimate their core temps. Say you measure 50C on a Mosfet case that runs 0.5A at 5V, its core is at 65.75C for example.
Check the temps on the electrolytics too, should not let climb near their rated temp as printed on their sleeves. Rule of thumb, when halving temp you quadruple long term reliability in electronics. Revisit the thermal plan if ever to box it up because then the ambient temp and convection are gonna get tougher issues IMHO. Nice build by the way, nice configuration. Enjoy.

Thanks Salas,

It seems I need add more heatsink to lower the temp. Yes, you are right, the fins facing down no good for radiating the heat but I have no choice .
Or, maybe, open a window underneath.

BTW, I like your regs, very thoughtful design with good performance. I bought three sets from the GB .

Regards,

Ian

[Salas]

The hot air has to rise vertical to the fins as it tends moving up so to efficiently convect heat from their surface. Better bolt it on a metal slab to increase the thermal absorbing mass than to make a down facing window. Nice that you liked them. Thanks.

[iancanada]

Originally Posted by Bunpei

May I ask which DPLL Bandwidth parameter is the best notch you obtained for the play of 192kHz/24bit PCM through the I2S signal path employing your FPGA (The minimum DPLL Bandwidth parameter to maintain a stable lock.) ? "Medium Low" or "Low"?

Hi Bunpei,

I have to set bandwidth to 'low-middle' to achieve long term stable lock with 192Khz I2S.

Ian

[bigpandahk]

Originally Posted by iancanada

I just got time this weekend playing with my ESS9018 DAC.
My system:
B&W 804, Pass A5, Pass 1.7, Buffalo III, LegatoIV,SalasShuntReg...

Hi Ian

I am also planning to use the SalasShuntReg to power the BIII. Just want to confirm my understanding is correct, you use 3 SSRLV to power the 3 trident and each set at 5.25V 100mA output? With such small current, why it generate so many heat (60 deg)???

[hochopeper]

Originally Posted by bigpandahk

Hi Ian

I am also planning to use the SalasShuntReg to power the BIII. Just want to confirm my understanding is correct, you use 3 SSRLV to power the 3 trident and each set at 5.25V 100mA output? With such small current, why it generate so many heat (60 deg)???

I think he's actually running +/- ssrlv to power the legato and a single +ve salas shunt to the VD terminals on the BIII which then feeds all 3 tridents. That was why I got confused when I first only saw 2 shunt regs (didn't spot the one hiding on the side) because powering BIII from the same supply as +ve rail to the legato would be a bit ......