Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 52 - diyAudio
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Old 14th May 2012, 10:33 AM   #511
qusp is offline qusp  Australia
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Quote:
Originally Posted by analog_sa View Post
Can you repeat this experiment feeding it i2s?
read his post, he already has

or do you mean an intermediate step feeding direct i2s without fifo?
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Old 14th May 2012, 11:11 AM   #512
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Originally Posted by qusp View Post
coolhead: so you already have the hiface? your proposed solution sure doesnt sound ideal, teleporter will not be jitter free either. IMO you would be better off getting lorien's Xmos USB->i2S board and connecting it directly to the fifo. it can be powered by USB or batteries, so shouldnt take up much space. even though the fifo definitely helps a great deal with solving jitter on MCLK, I think its better for it not to be there to begin with.
Hi qusp,
Yup, i am using the HiFace as transport for sometime already. I haven't order the Teleporter yet, being thinking about it for some time. I am still open to idea.
This is my plan: To fit all 4 modules (hiface, FIFO, BII, D1) into 1 casing would be ideal, but space is really a concern, I also have salas shunt regulators for them. Another option would be remove all power supply to another casing, as it has remote sensing, distance wouldn't be a problem.
I think for future flexibility also, it make sense to combine only 3 modules (FIFO, BII, D1) into 1 casing as I have the flexibility to try other transport in future.

PS: to make thing more complicate, I have a spare BII board, I can do duo mono also.

Thanks.

-coolhead
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Old 14th May 2012, 11:13 AM   #513
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It is obvious that a PLL recovered clock will greatly benefit from the FIFO. I was just wondering how much an I2S stream will be improved by the FIFO as compared to directly feeding it to the Sabre.
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Old 14th May 2012, 11:49 AM   #514
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Quote:
Originally Posted by analog_sa View Post
It is obvious that a PLL recovered clock will greatly benefit from the FIFO. I was just wondering how much an I2S stream will be improved by the FIFO as compared to directly feeding it to the Sabre.
fair question, suppose it depends on the quality of the i2s source
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Old 14th May 2012, 03:44 PM   #515
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Originally Posted by iancanada View Post
...

Next step, Iíll try the synchronized mode. But I have to remove the on-board CCHD950 100Mhz oscillator.

Have a nice week.
Very nice photos.
What setting for the DPLL did you use? for the different sample rates?
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Old 14th May 2012, 05:01 PM   #516
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Originally Posted by glt View Post
Very nice photos.
What setting for the DPLL did you use? for the different sample rates?
Thanks glt,

I use BIII default setting so far with all the switch jumpers at off position. I don't think this optimized for all the sample rates. What suggestion do you have?

I suspect, internally, ESS9018 has the similiar ASRC architecture with AD1896. But to run the 1896 at master-mode, you not only have to feed the I2S synced with the MCLK but also you have to set the corresponding jumper as well. For ESS9018, does it switch to sync mode(or master mode) automatically if the input I2S already sync with the MCLK(256,512 or 1024*fs)?
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Old 14th May 2012, 08:16 PM   #517
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Originally Posted by iancanada View Post
...

I use BIII default setting so far with all the switch jumpers at off position. I don't think this optimized for all the sample rates. What suggestion do you have?
use "lowest" Block 1 switches 5, 6, 7: On, OFF, OFF

When I use "lowest" and the source is a FPGA based I2S, I have to wait about one hour for the DAC to warm up; otherwise I get drop-offs (the DPLL looses synch)


Quote:
Originally Posted by iancanada View Post
...

I suspect, internally, ESS9018 has the similiar ASRC architecture with AD1896. But to run the 1896 at master-mode, you not only have to feed the I2S synced with the MCLK but also you have to set the corresponding jumper as well. For ESS9018, does it switch to sync mode(or master mode) automatically if the input I2S already sync with the MCLK(256,512 or 1024*fs)?
Automatically.

"Dustin: Again true but not the whole story. You can use the ASRC if you like - or not by simply clocking the XIN pin synchronously (at an integer multiple) to the BCLK. Then the ASRC drops itself out, reverting in this case to a more conventional method as the other DACs I'm aware of do."

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Old 14th May 2012, 09:48 PM   #518
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Originally Posted by glt View Post
use "lowest" Block 1 switches 5, 6, 7: On, OFF, OFF

When I use "lowest" and the source is a FPGA based I2S, I have to wait about one hour for the DAC to warm up; otherwise I get drop-offs (the DPLL looses synch)




Automatically.

"Dustin: Again true but not the whole story. You can use the ASRC if you like - or not by simply clocking the XIN pin synchronously (at an integer multiple) to the BCLK. Then the ASRC drops itself out, reverting in this case to a more conventional method as the other DACs I'm aware of do."

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Thanks, I'll give a try.
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Old 14th May 2012, 10:21 PM   #519
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Originally Posted by hochopeper View Post
Ian,

Nice photos! Had me confused for a second there looking at your power supplies, I didn't spy the 3rd salas reg that is hanging off the side of the heat sink.

Looks to me like you need a D1 to complete the set so you don't need to worry about any of those other DAC chips

Could you give any details on how you're terminating that i2s from u.fl into the pin female pin header? Have you had any thoughts on how to improve the situation at the DAC end of that interface? I've had thoughts about making a small pcb to convert pin headers to u.fl sockets and would appreciate your thoughts/experiences. I guess there is probably a bunch of other people in this thread looking to interface this board to DACs that don't always have ideal methods for connecting the i2s signal.
Thanks hochopeper,

Like my Salas shunts ? The temperature goes up to 60 degree C after 2 hours running, is that safe enough?

I just cut the 12" u.fl cables right in the middle, peeling off it at the end, separating the shield into a GND wire in a heat-shrink, then solder them into a pair of female pins and plug them into a 2 pos house. Making a adapter board with u.fl socket will be better for hookup, but I didn't see big difference on performance. The best way is solder the u.fl direct to the board as qusp did, but how about those already has the connecter soldered on board ?
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Old 15th May 2012, 01:27 AM   #520
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Quote:
Originally Posted by analog_sa View Post
Can you repeat this experiment feeding it i2s?
Quote:
Originally Posted by analog_sa View Post
It is obvious that a PLL recovered clock will greatly benefit from the FIFO. I was just wondering how much an I2S stream will be improved by the FIFO as compared to directly feeding it to the Sabre.
Hi analog_sa,

I did the test, the reslut was quite interesting.

When I switched the I2S source from FIFO output to S/PDIF board output(bypass FIFO), BIII still sounds wonderful, not as worse as I thought. However, when I switched the I2S back to the FIFO output, I heard the difference, very obviously, especially at high and middle-high range.

But it's just my personal feelings, so if it's possible, try it by yourself .

The FIFO XO was 22.5792Mhz CCHD957 for the test. ESS9018 was at ASRC mode(with 100MHZ CCHD950 for local MCLK).

Have a good night.
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