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Old 11th May 2012, 01:19 PM   #501
vzs is online now vzs  Europe
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Quote:
Originally Posted by KlipschKid View Post
[..] My first idea was to use an octal buffer like 74ac541 or 74F244 after the fifo - because the tda are in 8 pairs, each pair would get a driver. But I figured this would also negate some of the benefits of the fifo ?

Then ppl mentioned the logic level problem and I realised there were going to be too many reasons why it wasn't going to work well and I don't have the skills, knowledge or equipment to find and fix the problems[...]
I think you could simply replace 74HC125 with 74ABT125
These ABT logic families are quite good:
- 5V supply, with LVTTL compatible (VIH 2V) inputs
- High output capability: HIGH 32 mA; LOW +64 mA - seems more then enough to drive 16 x TDA1541 as it's specs says that digital input current for low (0.8V) -0.4mA to high (2.0V) 20uA so 16 x 0.4 = 6.4mA source capability.
- low propagation delays: ~3ns

You could give this a try.
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Old 11th May 2012, 01:31 PM   #502
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Quote:
Originally Posted by regal View Post
would be very useful to have a thrad for this topic, the powersupplies are the real hassel building a DAC.
.. thread starts at The Well Regulated Power Supply

Andrea
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Old 13th May 2012, 09:23 AM   #503
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Quote:
Originally Posted by vzs View Post
I think you could simply replace 74HC125 with 74ABT125
These ABT logic families are quite good:
- 5V supply, with LVTTL compatible (VIH 2V) inputs
- High output capability: HIGH 32 mA; LOW +64 mA - seems more then enough to drive 16 x TDA1541 as it's specs says that digital input current for low (0.8V) -0.4mA to high (2.0V) 20uA so 16 x 0.4 = 6.4mA source capability.
- low propagation delays: ~3ns

You could give this a try.
Thanks for the advice !
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Old 14th May 2012, 02:04 AM   #504
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Quote:
Originally Posted by regal View Post
qusp,

Believe me if Ian makes a board that plugs into a stereo pair of PCM1704 allows NOS and 352.8 with fifo crystal level jitter he will have a gold mine, there is little money in integrating these budget S-D chips because there are several other options out there (not quite as good as Ian's but damn close.) No one is calling you selfish you are a valuable member here, but look at the big picture. Do you see people spending 5 figures + on commercial Sabre's? Since the PCM1704 has become short supply with high end DAC makers dropping them, the prices of used totl commercial 1704 dac's have skyrocketed. Have you ever listened to a properly built PCM1704 (I mean no DF1704, top notch power supplies, top notch analog stage)?

The reason we are bringing up the 5V TLL is this second version is supposed to plug into the most popular digital filter ever (PMD100), if the level is an issue better to know now than before customers find out.

I also support increasing the price of the gb boards if needed, this from the start has potential to change the way we think about DIY DAC's.

Priority is simple and not as complex as you think:

1. stereo PCM1704 up to 8xfs
2. TDA1541 RBCD (check done complete)
3. ESS9018 (check done complete)
4. PMD100/SM5842 RBCD (close needs tested)
5. PCM56/AD1865/AD1862 RBCD

That pretty much covers all the high end DAC's made (I put the ESS on there for your impaired hearing Left off the TDA1543 as this from development was a budget chip, people have done creative things to overcome this but probably will always have to do so. This doesn't have to be a ******* match of my DAC vs yours, just 5 simple priorities that will change the way we DIYers build D/AC's forever.
Good ideas!
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Old 14th May 2012, 03:13 AM   #505
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Default FIFO and ESS9018(Buffalo III) hookup

I just got time this weekend playing with my ESS9018 DAC.
My system:
B&W 804, Pass A5, Pass 1.7, Buffalo III, LegatoIV,SalasShuntReg...

At beginning, I fed opt S/PDIF directly into BIII. It sounds pretty good, better than many other DACs at the same condition (without FIFO and good clock). That means the internal DPLL and jitter reduction is working. However, there are some click noises occasionally when Fs goes up to 192Khz.

Then I connected the FIFO I2S output into BIII via U.FL coaxial cables. Same opt S/PDIF into S/PDIF Interface Board. FIFO was powered by a battery pack with 22.5792 and 24.5760 CCHD957 attached on the Dual XO Clock board. The result was quite impressed. I donít want to say itís perfect, but I have to say itís very close to. I tried a couple of different kind of XO and found that the sound of ESS9018 still quite sensitive to the jitter from the input digital audio stream. I suspect the internal DPLL still has to trace the input clock to get lock with it. So, the clock jitter, outside the DPLL bandwidth, will still be introduced into DAC, which usually, the close in phase noise. While the final phase noise within the DPLL bandwidth will be decided by the performance of the internal DPLL(phase noise floor).
No click noise at all with same 192Khz input.

Next step, Iíll try the synchronized mode. But I have to remove the on-board CCHD950 100Mhz oscillator.

Have a nice week.
Attached Images
File Type: jpg Hookup.JPG (532.0 KB, 959 views)
File Type: jpg BIII.JPG (547.5 KB, 862 views)
File Type: jpg FifoAndBIII.JPG (559.8 KB, 780 views)
File Type: jpg I2Sconnection.JPG (470.7 KB, 756 views)
File Type: jpg SalasShunrReg.JPG (430.2 KB, 722 views)
File Type: jpg Running.JPG (328.2 KB, 349 views)
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Old 14th May 2012, 03:47 AM   #506
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Ian,

Nice photos! Had me confused for a second there looking at your power supplies, I didn't spy the 3rd salas reg that is hanging off the side of the heat sink.

Looks to me like you need a D1 to complete the set so you don't need to worry about any of those other DAC chips

Could you give any details on how you're terminating that i2s from u.fl into the pin female pin header? Have you had any thoughts on how to improve the situation at the DAC end of that interface? I've had thoughts about making a small pcb to convert pin headers to u.fl sockets and would appreciate your thoughts/experiences. I guess there is probably a bunch of other people in this thread looking to interface this board to DACs that don't always have ideal methods for connecting the i2s signal.

Last edited by hochopeper; 14th May 2012 at 04:07 AM.
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Old 14th May 2012, 04:20 AM   #507
qusp is offline qusp  Australia
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nice work Ian, you dont have to remove the clock for sync mode, you can just remove the ferrite that disables the regulator for it and then easy to solder a u.fl in front of the clock, between the XO and the 9018 there is pads or at least there was on bII for a resistor R17. pretty sure even on b3 there is a position to do this, check out Leon's upgrade manual. yes the clock will still be there and will be in HiZ mode, but it still works. however since you'll be using it with external clock all the time and have the tools to remove it go ahead. maybe heatsink the chip though while you are doing it.

yes Ian, you need to play with some other IV stages to take it the next level, the D1 is highly recommended =)
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Old 14th May 2012, 06:36 AM   #508
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Quote:
Originally Posted by iancanada View Post
I just got time this weekend playing with my ESS9018 DAC.
My system:
B&W 804, Pass A5, Pass 1.7, Buffalo III, LegatoIV,SalasShuntReg...

At beginning, I fed opt S/PDIF directly into BIII. It sounds pretty good, better than many other DACs at the same condition (without FIFO and good clock). That means the internal DPLL and jitter reduction is working. However, there are some click noises occasionally when Fs goes up to 192Khz.

Then I connected the FIFO I2S output into BIII via U.FL coaxial cables. Same opt S/PDIF into S/PDIF Interface Board. FIFO was powered by a battery pack with 22.5792 and 24.5760 CCHD957 attached on the Dual XO Clock board. The result was quite impressed. I donít want to say itís perfect, but I have to say itís very close to. I tried a couple of different kind of XO and found that the sound of ESS9018 still quite sensitive to the jitter from the input digital audio stream. I suspect the internal DPLL still has to trace the input clock to get lock with it. So, the clock jitter, outside the DPLL bandwidth, will still be introduced into DAC, which usually, the close in phase noise. While the final phase noise within the DPLL bandwidth will be decided by the performance of the internal DPLL(phase noise floor).
No click noise at all with same 192Khz input.

Next step, Iíll try the synchronized mode. But I have to remove the on-board CCHD950 100Mhz oscillator.

Have a nice week.
Hi Ian,
Nice finding. Thanks for sharing. I have a BII and am using the same connection (SPDIF -> FIFO -> SPDIF -> BII). Nothing much to worry about as it is just simple 1 line connection.
I'm thinking of using I2S input and sync mode for next upgrade. But the I2S connection going to be long as DAC + FIFO is in 1 casing, HiFace is in another casing. I am thinking of using Twisted Pear - Teleporter. This will be my next project before D1.

-coolhead
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Old 14th May 2012, 08:29 AM   #509
qusp is offline qusp  Australia
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have they made it so you cant use an external clock without removing it with the B3? with B2 you could just leave it unpowered by removing the ferrite that connects to the clock reg and connect the clock to the vacant pad at R17 (actually perfect for soldering a u.fl socket to as I did) the datasheet for the crystek would have you thinking this wouldnt work as the clock is in HiZ mode in shutdown, but this isnt the case it works fine.

since you'll be using the b3 with an external clock exclusively and have the tools to remove the XO fairly easily, its not a big deal I guess, but for the average user thats a bit annoying they've removed that ability to easily use an external clock with the update.

coolhead: so you already have the hiface? your proposed solution sure doesnt sound ideal, teleporter will not be jitter free either. IMO you would be better off getting lorien's Xmos USB->i2S board and connecting it directly to the fifo. it can be powered by USB or batteries, so shouldnt take up much space. even though the fifo definitely helps a great deal with solving jitter on MCLK, I think its better for it not to be there to begin with.

Last edited by qusp; 14th May 2012 at 08:34 AM.
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Old 14th May 2012, 09:13 AM   #510
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Quote:
Originally Posted by iancanada View Post
At beginning, I fed opt S/PDIF directly into BIII.

Can you repeat this experiment feeding it i2s?
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