Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

[KlipschKid]

Sounds like I'm going to have some fun finding the best set up ;-) Thanks for your help.

[qusp]

well if you put the fifo after the flipflop, where will you connect the masterclock that goes back to the source? to the flipflop? because the reclocked output of the fifo will not make sense to the source/transport with a flipflop in between

[regal]

Originally Posted by iancanada

Upgrading job finished finally. Two weekends were killedJ. New version will include the following features:

1. Optional 32bit left-justified output format support
Reason of this feature: To integrate FIFO with some DSPs or DACs which do not accept I2S input, for example, PMD100, SM5842, SM5843…
.

So to plug into a PMD100 we need a 256fs or 384fs clock (per the datasheet), is it as simple as replacing the 512fs clock that comes with the single clock board with a 11289.6mhz clock in order to use the PMD100, if not why the move to 512fs for the single clock (rbcd version) ?

[PET-240]

Actually qusp I concur, just not sure if the FIFO will take the 5V logic the 1543 uses. Hence saying ask Ian. Also agree it can't be all things to all people, but best we find out if it can without a smoke test. Would love to try with my terribledac. Which strangely is pretty good. Go figure!
Such are the joys eh!
Ian can you throw some light here please?

Thankyou linesman, Thankyou ballboys!

Drew.

[zinsula]

Originally Posted by regal

[...] is it as simple as replacing the 512fs clock that comes with the single clock board with a 11289.6mhz clock in order to use the PMD100, if not why the move to 512fs for the single clock (rbcd version) ?

If you read Ians post carefully, he writes that 512fs is a jumper selectable additional option. You can stick with 256fs. I do not see a problem...

[KlipschKid]

Originally Posted by qusp

well if you put the fifo after the flipflop, where will you connect the masterclock that goes back to the source? to the flipflop? because the reclocked output of the fifo will not make sense to the source/transport with a flipflop in between

Hi

MCLK does not go through the 74HC so this is one of the reasons why I'm wondering if it will work. I was thinking the MCLK would either be a problem or simply the fifo would not make much difference.

For example, the output of a WM8805 will not work into SRC4192/WM8741 y2 DAC if mclk is connected; only data, bclk, lrclk is necessary. Gnd is already shared through the psu.

I was also thinking that 16 ICs would create issues.

I can't see much point in putting it before the 74HC because I think this would negate much of the benefit.

I hadn't even thought of the logic levels.

Should I even try ?

Thanks for the help,

Tom

[regal]

Originally Posted by zinsula

If you read Ians post carefully, he writes that 512fs is a jumper selectable additional option. You can stick with 256fs. I do not see a problem...

Thanks but it looks like the PMD100 has the same 5VTLL requirements, needs 2.4V high min and 0.5 low min for logic input. Looks to be the same issue as the TDA1543

[PET-240]

This is where the fun sets in, have a geezer at the 1543 datasheet, see if you can use normal 3.3v logic, if 2.4v is the high minimum, it should be ok, the other though is check the current dac, the 74hc should have a 5v supply. See if it will run with a 3.3v supply. If the dac does and sounds the same on its current config, then the FIFO will be ok I reckon. If not, ask Ian whether the FIFO supports 5v logic out. Going by everything else The Man has done, it wouldn't shock me he has it covered. If not perhaps the FIFO output clock can also run the flip flop for the 5v change?
It "may" be as simple as a reg to the output. That "may" is speculation not fact.

And Tom, you have a pm.

Night night,

Drew.

[KlipschKid]

Hi,

TDA1543 digital input current is spec'd at low (0.8V) -0.4mA to high (2.0V) 20uA on page 7. I can't see any other info re input levels.

I'll get the DMM on the 74HC tomorrow and see what's up.

Thanks,

Tom

[qusp]

Originally Posted by PET-240

This is where the fun sets in, have a geezer at the 1543 datasheet, see if you can use normal 3.3v logic, if 2.4v is the high minimum, it should be ok, the other though is check the current dac, the 74hc should have a 5v supply. See if it will run with a 3.3v supply. If the dac does and sounds the same on its current config, then the FIFO will be ok I reckon. If not, ask Ian whether the FIFO supports 5v logic out. Going by everything else The Man has done, it wouldn't shock me he has it covered. If not perhaps the FIFO output clock can also run the flip flop for the 5v change?
It "may" be as simple as a reg to the output. That "may" is speculation not fact.

And Tom, you have a pm.

Night night,

Drew.

not sure about the dac side as i'm not really familiar with these old hands, but no, the fifo itself does not and will not support 5v, however Ian is working on this for the level shifting daughterboard, but thats a ways off

any reason why we are covering this ground all over again? (not directed at you specifically)