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Old 22nd April 2012, 07:50 AM   #431
zinsula is offline zinsula  Switzerland
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Hi Ian, very good. I'll look into these pictures, but not yet.
My nice will be here today and i have to help her solder a kit....a roboter kit. DIYRobot....

As for new functions of the fifo, are they reprogrammable in circuit?
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Old 22nd April 2012, 03:44 PM   #432
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Quote:
Originally Posted by zinsula View Post
Hi Ian, very good. I'll look into these pictures, but not yet.
My nice will be here today and i have to help her solder a kit....a roboter kit. DIYRobot....

As for new functions of the fifo, are they reprogrammable in circuit?
The I2S to PCM daughter board is based on CPLD/FPGA, all this kind of designs are re-programble. Integrating it into FIFO board is possible, but I don't think it's a good idea because the output interface and connectors are different.

Enjoy your weekend.
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Old 22nd April 2012, 09:07 PM   #433
vzs is offline vzs  Europe
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Hi Ian,

Impressive progress. I reviewed your description (2 to 6) and the waveforms and everything looks good to me:
- I like that you added 16bit support
- The naming is clear like that (at least for me)
- Simulation waveforms looks good
- Leading clock selectable - too many goodies

Quote:
Originally Posted by iancanada View Post
[...]FIFO board will be upgraded to support left justified format(which has nothing to do with this board)[...]
Seems a logic decision not to put it on the converter daughter board.
How did you think it would work?
- I2S in and selectable I2S out or Left Justified Out
or
- selectable I2S in - I2S out or Left Justified in - Left Justified out

Thanks and enjoy your weekend (what is left),
Zsolt
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Old 22nd April 2012, 10:19 PM   #434
zinsula is offline zinsula  Switzerland
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Hi Ian!

Quote:
Originally Posted by iancanada View Post
The I2S to PCM daughter board is based on CPLD/FPGA, all this kind of designs are re-programble. Integrating it into FIFO board is possible, but I don't think it's a good idea because the output interface and connectors are different.
A little misunderstanding here....i was talking about this:

Quote:
Originally Posted by iancanada View Post
[...]FIFO board will be upgraded to support left justified format(which has nothing to do with this board)[...]
My question was if this can be updated easily on an existing FIFO board.

Oh, and for the different waveforms, they look good. I agree with about everything Zsolt has already stated. Nice there is 16bit also, who knows....

Anyway, hope you had a good weekend!
Ciao, Tino
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Old 23rd April 2012, 12:39 AM   #435
glt is offline glt  United States
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Originally Posted by iancanada View Post
Hi Andrea,

In the above post, I'v already confirmed you can feed I2S signals directly from CDPro into FIFO. . My FIFO could handle I2S with sck running at 48*fs.

Regards,
Does this mean that it also supports 32*fs?
(CDROM, VSLI Solution audio chips)
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Old 23rd April 2012, 01:33 AM   #436
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Does this mean that it also supports 32*fs?
(CDROM, VSLI Solution audio chips)
Yes, current version already support sck run at 32*Fs. But it standard I2S, not the right justified.

I remember you need a rigtht-justfied input tapping from a CDROM? 16bit of 24bit?
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Old 23rd April 2012, 04:16 AM   #437
glt is offline glt  United States
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Hi Ian,

The vlsi audio chip (http://www.vlsi.fi/en/products/vs1053.html) are 32*fs I2S. The cdroms are 32*fs. Last I experimented with a TI ASRC, it required setting it as right justified. I'll have to get myself a logic analyzer to make sure.

But DACs support I2S, RJ, LJ so having these options, plus 32*fs, 48*fs and 64*fs clock will make it a "universal" device
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Old 23rd April 2012, 02:40 PM   #438
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Hi Ian,

The vlsi audio chip (VLSI Solution-VS1053 - Ogg Vorbis / MP3 / AAC / WMA / FLAC / MIDI Audio Decoder / Encoder Chip) are 32*fs I2S. The cdroms are 32*fs. Last I experimented with a TI ASRC, it required setting it as right justified. I'll have to get myself a logic analyzer to make sure.

But DACs support I2S, RJ, LJ so having these options, plus 32*fs, 48*fs and 64*fs clock will make it a "universal" device

Good point glt, but the right justified is kind of word length related, usually it's 16 and 24 bit. Is that works for you?
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Old 24th April 2012, 11:40 AM   #439
qusp is offline qusp  Australia
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building up 'breadboard' for testing different options, clocks, references, regs IV etc for the dac that will drive my tweeters, the woofers are already covered with the NTD1 with another ackodac. some progress below, should power it all up tonight or tomorrow. I will try running Titan through the fifo as well as direct. it has its own clock fanout buffer and smaller fifo afaik and some rather nice clocks, so should be an interesting comparison, titan is capable of higher bandwidth than the fifo is in its current state, so i'll stick to 192 or below for the tests. the platform is normally mounted above the IV with the NTD1 thus the fairly useless set up here, though it will provide another layer of space for batteries, references etc for the rest of the testing


yes the 4 channel dac will be a 2 box affair with transformers and preregulators, battery charge circuit, along with some control circuitry in one case and the rest, DC onwards, dacs, input circuitry and output stages in the other.

its a pretty crazy build even for these 2 channels, first up i'm driving the wire BAL-BAL headphone amp directly and have altered the input circuit slightly to allow current mode coupling

please excuse the messy bench and rough and ready layout, i'll be switching things in and out so its only temporary and no thats not earwax on the cotton buds, its cardas rosin flux everything is currently floating in this build too, so thats another thing i'll be optimizing with this, the analogue stages including those in the dac should have a common ground reference, but the rest can float really as its either batteries, or a dedicated secondary winding for every consumer, so we'll see. the regs on the ackodac are all choke input so they float too


dacs arent what they used to be hey? ha
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Old 24th April 2012, 01:13 PM   #440
qusp is offline qusp  Australia
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to clarify, the ground plane is segmented, not all regs have a dedicated segment so I guess pairs of left/right are floating together. missed the edit to add this above, sorry
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