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Old 20th April 2012, 01:00 PM   #421
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Quote:
Originally Posted by andrea_mori View Post
I've seen the datasheet, 2.1168 x n.
Spdif in not the best solution, I2S is definitely a cleaner solution, but if no other solution I'll use spdif.

Well, I'm waiting for Ian impression about this.
Hi Andrea,

In the above post, I'v already confirmed you can feed I2S signals directly from CDPro into FIFO. . My FIFO could handle I2S with sck running at 48*fs.

Regards,
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Old 20th April 2012, 01:14 PM   #422
vzs is offline vzs  Europe
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Quote:
Originally Posted by iancanada View Post
[...]Any word length between true 16bit to true 32bit is working[...]
Thank you for your response, impressive.

Actually you wrote this in the manual IanI2SFIFOV1.0.pdf at I2S input: "44.1 KHz, 48 KHz, 88.2 KHz, 96 KHz, 176.4 KHz, 192 KHz - 16bit, 24bit or 32bit" but I thought these are data bits not word lengths.
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Old 20th April 2012, 01:56 PM   #423
regal is offline regal  United States
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Originally Posted by vzs View Post
Hi Ian,
It looks promising. I also have some remarks:

Five jumper selectors
- it seems that beside jmpstopclk you used negative logic to set their function
- according to the simulations they look correct, but this negative/positive logic mixing is a bit confusing. Would be nice to be consistent and use either negative or positive logic for all

Data and clock lines for all three images
- is confusing that the MSB of the right channel starts with 0 while the MSB of the left channel with 1; so it looks like they are delayed by one clock, but probably not
- for stopped clock mode I also count +1 clock but I don't think this is an issue since only the last X bits will be transferred to the parallel DAC registers (after latch has gone low)

Concerning reclocking I share zinsula's opinion from #388.

A suggestion about board layout: it would be nice to be stack-able above the clock board - probably same size. If it's input would come from the FIFO board then the input connector could be in same position as on the clock board.

Thanks, Zsolt
Thing about it is both PMD100 and SM5842 were typically fed from a CS8412 with Mo=0, m1=1, M2=0, M4=0, which is phillips I2S. I don't remember there being issues.


If the next Fifo is going to offer Sony format, why not offer splitting the data into left and right as well, and shifting registers for different bitdepths.


If it could be flexible enough to plug directly into a pair of PCM1704, PCM56,or AD1865, it would be a huge boon to the whole NOS scene.

Also if we could plug in the Fifo to a pair of PCM1704's at 352.8 we could start making our own 8x oversampling algorthms with the computer.

As far as upgrading the 11289.6 clock on the standard Fifo, I think the Tent 24,37 XO-DIY, is the only option. There seems to be no 256fs clocks on the market that will run at 3.3V.
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Old 20th April 2012, 01:57 PM   #424
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Quote:
Originally Posted by wktk_smile View Post
Hi, Ian

Your FIFO+reclocker combined with Sabre dac is really impressive, especially when synchronous mode between the dac and reclocker.

When I first fired up SDTrans384 - FIFO plus reclocker( U1 is replaced with NDK NZ2520SD ) - Buffalo2 setup, I immediately noticed this obviously outperforms SDTrans384 - Buffalo2 combo.
Side by side comparison was never needed.

Now I can hear more low-level informations more easily and feel as if near the everything some more precise - bass are better controlled, less harsh Hi, and so on.

Really good job indeed, and I'm glad to see you still seek more improvement and versatility...


Thanks!
Hi wktk_smile,

You are the first guy who implements the integration of FIFO and Sabre32 DAC( or Buffalo) I know so far. Especially running it at synchronized mode. Congratulations! I suspect a lot of people are waiting for this good news.

Thank you so much for sharing your experience. I'm very interested in your hookups. Could you please let us know a bit more details? or some pictures? With the synchronized mode, what frequency of your NDK XO did you use? Actually the Buffalo III I bought just arrived yesterday. Hopefully I could try it next week. I have to focus on upgrading the FIFO and design the new PCM daughter board now.

Regards,
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Old 20th April 2012, 02:31 PM   #425
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Quote:
Originally Posted by regal View Post
Thing about it is both PMD100 and SM5842 were typically fed from a CS8412 with Mo=0, m1=1, M2=0, M4=0, which is phillips I2S. I don't remember there being issues.
You can fed I2S into PMD100 or SM5842 but you will loose the LSB and the left/right channels will be reversed. I've done that accidentally so I know. CS8412 supports the right justified format for 16bit or 18bit (no.5 and 6) which is indeed a correct format for both PMD100 and SM5842. I'm using CS8414 with AD1865 in NOS mode so I've sweat on these manuals a lot

The converter board Ian is preparing will support several output formats, including for those DACs you mentioned and the Left Justified format for the digital filters which don't support I2S.

Last edited by vzs; 20th April 2012 at 02:33 PM.
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Old 20th April 2012, 04:46 PM   #426
guido is offline guido  Netherlands
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For I2S, the PMD100 needs a flipflop for WCLK. It's in the datasheet...
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Old 21st April 2012, 10:39 AM   #427
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Quote:
Originally Posted by iancanada View Post
Hi wktk_smile,

Thank you so much for sharing your experience. I'm very interested in your hookups. Could you please let us know a bit more details? or some pictures? With the synchronized mode, what frequency of your NDK XO did you use? Actually the Buffalo III I bought just arrived yesterday. Hopefully I could try it next week. I have to focus on upgrading the FIFO and design the new PCM daughter board now.

Regards,
XO is NZ2520SD-22.579200M-NSA3449C, and later I also replaced U2 with 24.576mhz one.

they are not fast as ES9018's MCLK, but fine for actual use for playing up to
96khz pcm. While playing 176.4khz and 192khz, bypassing OSF mode was required.
Attached Images
File Type: jpg IMG_5511A.jpg (163.2 KB, 570 views)
File Type: jpg IMG_5512B.jpg (149.5 KB, 558 views)
File Type: jpg IMG_5513B.jpg (76.5 KB, 548 views)
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Old 21st April 2012, 10:55 AM   #428
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Although stock XOs may be "generic" ones, I felt they are not bad.
Even with stock XO, FIFOboard + reclocker gives good results.

Last edited by wktk_smile; 21st April 2012 at 10:59 AM. Reason: grammatical correction
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Old 21st April 2012, 01:18 PM   #429
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Quote:
Originally Posted by wktk_smile View Post
XO is NZ2520SD-22.579200M-NSA3449C, and later I also replaced U2 with 24.576mhz one.

they are not fast as ES9018's MCLK, but fine for actual use for playing up to
96khz pcm. While playing 176.4khz and 192khz, bypassing OSF mode was required.
Hi wktk_smile,

Thank you for the pictures. Very impressed.

Actually, the dual clock board has a reserved double speed mode which could run 45.xxxx and 49.xxxx MHz XO for ES9018 or Buffalo DAC to make us more happy, especially for the synchronized mode. I'll publish the setting document after I conformed that on a real Buffalo III dac. Maybe I still need to inquire you when I go the hookup.

Quote:
Originally Posted by wktk_smile View Post
Although stock XOs may be "generic" ones, I felt they are not bad.
Even with stock XO, FIFOboard + reclocker gives good results.
Yes, at least that is the original clock from a crystal, don't need to trace another input clock.

Have a nice weekend.
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Old 21st April 2012, 10:07 PM   #430
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Default New I2S to PCM converter board design in synchronize mode

Quote:
Originally Posted by zinsula View Post
I agree with you and Zsolt that as only the last n bits will be clocked in before latching. You clearly know more about all that high speed logic stuff and if you think that it has some advantages, leave it.


No problem. It was just me which did not get naming and status of the bits. As long as the combinations are safely described and not ambiguous (logic wise) it's OK.


This is a though one for me. I believe using 4 more clocks will be safe for both. As the DATA and LE lines are quiet anyway during conversion, I believe there is not much performance loss.


Very good. Will you use single flip flops (Potato?) for the sensitive clocks (LE and Bit clock?)



Actually, it helped me identify if all is OK (L/R difference)


Good, so the (dual) clock board is needed to select the correct clock freq and to provide the clean MCLK?
Will we still have the actual functionality on the dual clock board, i.e. the indication of fs and MCLK multiplicator?


Do you mean if you feed the FIFO with Sony format? Is that word length 24 bit, left justified, MSB first after word clock change, and Word Clock high = left channel?
Or do you mean that it should output Sony format, to feed eg. Andrea's SM5842?

All in all, great job Ian. thank you.
Quote:
Originally Posted by vzs View Post
I would leave the "leading clock" for the reasons you mentioned, better to be on the safe side.


With 4 trailing clocks only PCM1702 would benefit of the stopped mode operation while for PCM1704 would be similar to continuous clock mode.
As PCM1704 is the newer and seems to be used by more diyers I would better support this - so to have 2 trailing clocks. But it's all one for me.


You would make fellow diyer andrea_mori happy

If you add another output format I have some arguments for the Left Justified over Sony Format:
- as I understood Andrea wants to connect the FIFO between a CD-Pro and his Sony Format input DAC board. As the CD-Pro outputs 16bit I2S you would have to add 16bit support to the converter to output a correct right justified format for him
- Left justified differs from I2S very slightly: latch should be negated and shifted with one clock - so needs less logic to implement
- digital filters from NPC, TI/BB, PMD all support Left Justified with multiple bit lengths, while Sony Format is supported only for 16bit data; except for NPCs
- the downside is that Andrea would have to make some minor pcb adjustments to set his board for Left Justified format - but hey, this is diy
All in all I'm fine with or without it.

Thanks, Zsolt
Hi Zsolit, Hi Vzs,

It took me quit a bit time revising the I2S to PCM daughter board design from SCK driven to MCLK driven. New design is 100% synchronized state machines. The performance get big improved. Now I can run 384KHz with 256Fs on the board. But I don't know which USB I2S could support.

1. 100% synchronized FPGA design with max inject MCLK going up to 127Mhz.

2. three word length jumpers, 16,18,20,24 bits output selectable

3. three option functions jumbers:
continue clk
tailing clk
leading clk
all jumbers are negative logic internally. Please note the new names.

4. I attached some simulation waveforms with different jumber setting.
all the simulations were run at 50Mhz MCLK for 128Fs. 100Mhz 256Fs got the almost the same result.

5. The tailing clk is reduced from 4 to 2 making PCM1704 benifit from it.

6. The leading clk new becomes optional.

Please let me know for any comment. FIFO board will be upgraded to support left justified format(which has nothing to do with this board).

Have a nice weekend.
Attached Images
File Type: jpg 18BitAD1865.jpg (206.1 KB, 513 views)
File Type: jpg 20BitAD1862WithLeadClk.jpg (206.7 KB, 491 views)
File Type: jpg 20BitPCM1702WithContinueClk.jpg (222.1 KB, 95 views)
File Type: jpg 24BitPCM1704WithTailClk.jpg (219.2 KB, 98 views)
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Last edited by iancanada; 21st April 2012 at 10:10 PM.
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