Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

[goldkenn]

Originally Posted by simmconn

The problem is the RAM size. Large SRAM is not cheap and not easy to come by. Or you can go DRAM with a slightly more complex memory controller. Since the RAM size needed is the function of supported sample rate, bit depth and clock frequency difference, one can calculate how much RAM is enough.
500ppm is a good, practical starting point, but I would opt for 1000ppm, which is IEC60958 standard for S/PDIF streams. In order to support a stereo 192KHz/32bit PCM stream at 1000ppm clock frequency error without FIFO overflow over a continuous 1.5 hour playback (gap-less), you'll need about 8MB (64Mbit) of memory.

Considering even a typical FIFO interface already not simple to general DIYer, anyone like you and now Ian willing to start the game, should be not mind about the price of SRAM, although cost still matter, but think about all time and effort which we could use for earn much, the SRAM become nothing...... Sorry for my poor English, I hipe I sucessfully express my thoughts and all of you understand.

[iancanada]

Originally Posted by qusp

looking good Ian, i too prefer batteries for clock and also use them for powering the analogue sections of the dac (3v3 for AVCC L/R and 1v2 for analogue reference) but I use LiFeP04 by A123. what battery chemistry are the Cyclon?

beautiful speakers btw, the B&W are some of the best i have ever heard. Thats a pretty serious Disk spinner you have there, is that face actually made of stone haha, or just a finish on the alloy. it looks like it opens up Star Trek style.

Hi qusp, sorry the late reply. I was out of town on this long weekend. The Cyclon battery is a kind of lead-acid battery with special internal construction. It's one of the few which could touch the medical grade due to its wide temperature range, long life, high current and low noise. The LiFeP04,you recommended, looks has higher current density and smaller size, I'd like to try it later on. Yes, the KRELL KPS 20i/L CD transport was one of the top of the line in the 90's. Very clasical like a mailstone. This model is very special one, internally, it integrated a CDM9pro CD tranport unit and a 4*PCM63K DAC unit together, but at same time, they independent from each other. I bought it used for more than $5K five years ago just because I need a reference DAC and a reference SPDIF source for the developing of my CD transport project. So are the B&W 804 speakers. All of them are also usefull for my current I2S FIFO project now. Without listening compare with those top toys, I even don't know how far I could go. Thanks again for the follow up. Have a good night. Ian

[SoNic_real_one]

I am glad that there is somebody that thinks like me around here. When I was discussing on another thread that the FIFO cache is the only good way to eliminate jitter, I was told that CD controllers have enough FIFO (yes, all 4kB of it ).
Unfortunatelly, I don't have the spare time to do to much DIY projectes like I used to when I was younger.
Good luck with your project, looks like you are on the right path.

[iancanada]

Originally Posted by simmconn

Glad to know that someone has the similar interest. Nice board!...

Hi Simmconn, Thank you for sharing your experience with us. You did great job, Simmconn. Very nice board design. Congratulations!
You must be a very experienced electronics design engineer. To achieve that project, you need a lot of knowledge and skills such as FPGA design, signal processing,circuit design, PCB layout, embeded processor design as well as the full range of digital audio technologies. I'm very glad to know that somebody else in the world had the similar idea and interesting with me. At least, it proved, I'm not the alien ).
My idea of design a I2S FIFO started from 5 years ago. At that time,I was developing my CD transportat. During the test, I found that the different clock source of the CD transprot result in great difference on the sound quality.But no matter how much care I took on the clock, there was still some kind of barrier blocking the improvement of the sound quality of play back on the DAC side.
So I went a bit deep and did some reserach on the master clock tree. it was like this: master clock -> DIT -> SPDIF driver -> pluse transformer -> coaxial cable -> pluse transformer -> SPDIF receiver -> DIR -> PLL recover clock -> DAC; The clock route was too long and each section would introduce big amount of additive jitter. Especially the flip-flop inside the DIT chip and the SPDIF driver except the master clock itself. Although the high range jitter of the recovered clock was determined by the PLL, but the PLL still tracing and locking the low range of input clock together with the jitter below the corner frequency. So finally I realized that the solution would be introducing a brand new low jitter clock to isolate the recover clock and feed the DAC directlly without any buffer and flip-flop in between. The answer was asynchronous I2S FIFO.
I didn't launch this project until last Christmas vacation. Since then, I started this I2S FIFO job from the verlog coding. Step by step, I wrote different modules and simulated and ran them one by one on my CycloneIII EP3C16 board. I did a lot of simulation and test before I went the real hardware.
Yes, you are right, this project is not limited to pure I2S FIFO. With the clock board, it is the I2S FIFO to boost the DAC; with the DIR, it become the SPDIF receiver with the buildin FIFO and low jitter clock; with the DIT and DIR, it become the SPDIF FIFO; integrated with DAC, it become the high performance low jitter DAC with buildin FIFO; with the MCU, it become the digital audio front end. There are a lot of extension in front of this project.
On this projcet, one of my opinion is: improtant of the important is the clock. Now, I have already switched my focus point from FIFO design to clock board design and looking for better clock source. Because the FIFO is only a logic function,but what really influence the sound quality is the low jitter clock.
Simmconn, just hope everything is well with you now. You should continue your project and keep bringing the 'fun' both to you and to us.
It was very nice meeting you in this thread. Thanks again for all. Take care. Ian

[iancanada]

Originally Posted by SoNic_real_one

I am glad that there is somebody that thinks like me around here. When I was discussing on another thread that the FIFO cache is the only good way to eliminate jitter, I was told that CD controllers have enough FIFO (yes, all 4kB of it ).
Unfortunatelly, I don't have the spare time to do to much DIY projectes like I used to when I was younger.
Good luck with your project, looks like you are on the right path.

Your point of view is correct, SoNic_real_one. Totally agree with you. 4KB and 4MB make big difference .
Thank you and have a good night. Ian

[simmconn]

Originally Posted by goldkenn

Considering even a typical FIFO interface already not simple to general DIYer, anyone like you and now Ian willing to start the game, should be not mind about the price of SRAM, although cost still matter, but think about all time and effort which we could use for earn much, the SRAM become nothing...... Sorry for my poor English, I hipe I sucessfully express my thoughts and all of you understand.

In the DIY community, the development effort is usually not amortized into individual units, which makes the part cost the primary concern. Having a low total part cost would just benefit everyone, right?

[iancanada]

Originally Posted by goldkenn

Today CAS become more and more popular, considering a DAC may not just or even no more for CD playback, and more and more 24/88.1 or higher rate files could buy or share online, I will suggest do more test for 24/88.1 or higher rate playback, plus maybe even upgrade the FIFO support up to 384KHz, since 32/384 USB DAC or USB-I2S interface starting appear in the market already.

Hi Goldkenn, thank you for your reply.
Actually, the FIFO section just isolate two I2S domain and has noting to do with the Fs. You can feed it with 384K/32 bit stream without any problem if you could provide suitable mclk. (only the mclk decide the Fs, not the FIFO). Accodring to the simulation result, the max mclk of this FIFO could go upto 120Mhz.
The clock boards I'm cooking right now will support upto 192Khz/24/32 Fs, for sure. Talking about 384KHz/32... actuall I could... but I don't have much PCB space...just let me think about it. Thanks, Ian

[iancanada]

Originally Posted by guido

I'm wondering about live concerts, in case there are no silences inbetween the songs. What happens if the fifo runs full or empty ??

Very good question, Guido. I'm afraid if the FIFO is empty, it will sound like repeating a word(around 1s for 44.K), and when it full, it will sound like short a word(around 1s for 44.K). Meanwhile, no pause,silence and other noise. Just imagine if you have a cassette, cut 1secnd length or extend it with 1 second copy, would be the same thing as FIFO full and empty.
When you play the continue live concerts, this will happen every couple of hours if the sampling clock is not that bad(with 100ppm frequency tolerance).

PLL is another solution. According to my quite limited knowledge on this issue, the key thing should the bandwidth. If you reduce that bandwidth to a certain level, you might still need a FIFO to buffer the data, but may not that big ...
Maybe I'm wrong or you have some good idea..anyway, good luck to your project. Have a good night. Ian

[simmconn]

Originally Posted by iancanada

Hi Simmconn, Thank you for sharing your experience with us. You did great job, Simmconn. Very nice board design. Congratulations!
......

Simmconn, just hope everything is well with you now. You should continue your project and keep bringing the 'fun' both to you and to us.
It was very nice meeting you in this thread. Thanks again for all. Take care. Ian

Thank you, Ian. You must have realized that even though the idea is straight forward, it takes a lot of time and effort to make it happen, not to mention the scope of knowledge it requires.

I, too, realized that the clock is critical. However, with often misleading specifications published by the mfgs, the quality of clock is somewhat subjective (as a matter of deciding who you choose to believe ). One can make a multi-stage crystal-filter based oscillator, or have a digital audio frequency OCXO custom made, or even use a Rubidium clock (not that I recommend it, though). For the most 'fun-factor', a FIFO board would be BYOC (bring your own clock).

What made me a bit skeptical about a piece-meal I2S board approach is that a less-than ideal wiring (especially the digital signals) can easily counter the benefit of the FIFO. Using an SMA tee connector on the clock line seems to indicate that you are not an RF engineer. Me either. I learned a lot from the folks at diyhifi, but still too little to tackle the clock issues.

By the way, I noticed that the SRAM on your board is 256kx16 (4Mbit=512kByte, not 4MB). You might want to use the lower case 'b' when mention it.

[regal]

Consider the intrinsic jitter of any complex chip you are using. In this design say we have an incredible transport with documented 3ps jitter delivered to the DIR9001. After the DIR9001 we will have 53ps (+- based on the mckl per the datasheet), this intrinsic jitter is always added and has nothing to do with the corner frequency, above the corner frequency is where the 3ps from the transport will be passed (worst case).

No we have your FIFO, feeding your chip a high quality clock, great now we have jitter equal to intrisic jitter of the FIFO chip + clock jitter. Now I'll bet a few dollars the chip used here has more intrinsic jitter than a 9001 which was specifically layed out for digital audio. So I guess what I am saying is if your transport is very good, your FIFO will probably add overall jitter.

Solution is easy, simply reclock the output with the same crystal, this will eliminate the FIFO's potentially high intrinsic jitter. This technique has been used for years dealing with CD decoders, it works and should be considered here.