Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

[andrea_mori]

Originally Posted by iancanada

Hi Andrea,
1. For sure, you can take I2S signals from CD Pro and you don't need any re-clocking before feeding into FIFO. It is 'redundant' . Because FIFO will isolate all the input jitter.
2. Interfacing I2S with PCM63, you have to use a little converter board. PCM63 do not directly support i2S.
3. From 5842 doc, I found it do not support i2S input. It's kind of 'SONY' format. In this case, maybe you need a special version of FIFO to output that format.

Can you implement that format?
I would like to buy the kit to feed SM5842, in oversampling PCM63 DAC.

Andrea

[iancanada]

Originally Posted by zinsula

I think your timing diagram for the AD DAC's look good, Ian.

If I might suggest one more thing:
Would it be possible to create a second DATA line per channel, which has the bits inverted?
Would be cool...easening a balanced DAC design. PCM1704 adopters don't need it though....

Hi my friend. We got same idea! I was planning to include inverted data signals for both of the channel just in case somebody need running the DAC at mono mode. I'll use a 8 bit low jitter GHZ flip-flop for re-clocking which will have enough lines for all the signals.
Cheers,

[iancanada]

Originally Posted by andrea_mori

Can you implement that format?
I would like to buy the kit to feed SM5842, in oversampling PCM63 DAC.

Andrea

Hi Andrea,
I'm thinking about out how to upgrade the verilogHDL software of my FIFO. Which will include the optional left-justify(sony format) output for working with some digital filter. The optional left-justify and right-justify input, maybe. Just hope it could catch up with the second GB run. Hardware will keep no change.
Regards,

[zinsula]

Originally Posted by iancanada

[...]I was planning to include inverted data signals for both of the channel just in case somebody need running the DAC at mono mode.[...]

Great!

Originally Posted by iancanada

[...]I'll use a 8 bit low jitter GHZ flip-flop for re-clocking which will have enough lines for all the signals.[...]

Isn't that a bit dangerous regarding cross coupling of the signals, and introducing jitter this way?
For the data lines, i see no problem at all, but for LE and BCK perhaps?

[andrea_mori]

Originally Posted by iancanada

Hi Andrea,
I'm thinking about out how to upgrade the verilogHDL software of my FIFO. Which will include the optional left-justify(sony format) output for working with some digital filter. The optional left-justify and right-justify input, maybe. Just hope it could catch up with the second GB run. Hardware will keep no change.
Regards,

Ian,

I would like to order FIFO kit, but I'm a bit confused.
As I said I want to feed FIFO kit directly from CD PRO I2S, then I would like to take I2S output and MCLK and feed digital filter NPC SM5842.
You tell me that SM5842 do not accept I2S format data, while Rregal in a previous post said that it can do it.
I found on the web the attached schematics that interface I2S with 5842, so I believe you're right.

BTW do you think that I can feed 5842 using this schematics?
If yes, do I need FIFO board only?
What frequency oscillator?

Anyone can help me?

Thanks in advance
Andrea

[vzs]

Originally Posted by iancanada

I attatched the updated timing plots, taking example for both AD1865 and PCM17xx. Let me know for any problem.

*please don't care about the LL,LR signals at the next word, I forgot changing them on the plots.

They look good to me.

I don't want to split hairs about stop clock mode of PCM17XX but during conversion of a PCM1704 the clock will still run. To have a non-plus-ultra converter another stop clock timing is needed where the bit clock is stopped 2 cycles after the latch goes down, I think.

One more note: for the running clock mode I think the attached timing is good for all the mentioned DACs. What do you think?

I almost forgot I would also need and inverted data signal as the single ended preamp after my I/V inverts the phase. Nice idea to support it

Thanks.Zsolt

[vzs]

Originally Posted by iancanada

Hi Andrea,
I'm thinking about out how to upgrade the verilogHDL software of my FIFO. Which will include the optional left-justify(sony format) output for working with some digital filter. The optional left-justify and right-justify input, maybe. Just hope it could catch up with the second GB run. Hardware will keep no change.
Regards,

Some hair splitting to prevent confusion about formats: the sony format is right-justified format (aka LSB-Jusitifed). I checked several digital filters and at least the Nippon Precision's SM58XX, DF1704 and PMD100 support this right-justified format.

I wish I know Verilog/VHDL; it would had helped me alot

[zinsula]

Originally Posted by vzs

[...]One more note: for the running clock mode I think the attached timing is good for all the mentioned DACs. What do you think?[...]

Not sure what you mean with running clock mode. The timing is OK, if you use right justified data.

But...for AD1865 and AD1862, I really would advise to stop the clock in any case before the LE line goes low. It will improve jitter performance and would be the preferred method when this logic is feeded with left justified I2S data (as is output from FIFO).

[vzs]

Originally Posted by zinsula

Not sure what you mean with running clock mode. The timing is OK, if you use right justified data.

But...for AD1865 and AD1862, I really would advise to stop the clock in any case before the LE line goes low. It will improve jitter performance and would be the preferred method when this logic is feeded with left justified I2S data (as is output from FIFO).

I meant a format with a continuously running bit clock, which is the basic operation mode of the DACs we discussed so far - that's why I think we should have it.

[zinsula]

So you mean to have it as an optionally selectable format, as would be the stopped clock operation?
Then it's OK of course :-)