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Old 13th April 2012, 07:51 AM   #341
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Quote:
Originally Posted by iancanada View Post
If I did this projcet, I'd like to use a CPLD.

1. It will cover both AD1865(18bit) and AD1862(20bit), as well as PCM63(20bit).


Would it be possible to add 24 bit as well. Please
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Old 13th April 2012, 08:20 AM   #342
zinsula is offline zinsula  Switzerland
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I planned to construct this with 3 Shift registers per cannel and some XOR and NOR gates.
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File Type: gif FIFO I2S to AD1862.gif (177.3 KB, 554 views)
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Old 13th April 2012, 09:33 AM   #343
vzs is offline vzs  Europe
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Originally Posted by iancanada View Post
I attched the possible timing waveform (take AD1865 for example). Please let me know if there is any problem.
To have the correct sample for the L and R you should shift everything as in I2StoAD1865converting.jpg

I reviewed the timing diagram of PCM63, PCM1704 and AD1865 so I will refer only to these.

Until now I kinda misinterpreted the functionality of LE. It must be set high one (AD1865) or two clock cycles (PCM63/1704) before we want to latch data into the DAC, but it can be kept high for more cycles. For stopped clocked operation PCM63/1704 specify that: "Latch Enable must remain low until after the first clock cycle of the next data word to insure proper DAC operation" - see PCM63 timing.png

The stopped clock operation looks interesting and its probably beneficial, however AD186X doesn't specify this mode of operation at all, but I think it could work fine if we follow the correct timings.
Some thoughts about timings:
- DAC output changes state for PCM63 and AD1865 when LE goes negative, while for PCM1704 two clock cycles after LE goes negative
# With a switch we could select the stopped clock format - basically to have two clock cycles after LE or not
- The minimum width of LE high differs among these
# A good compromise could be to set LE high two/three clock cycles before it should go low
- For the above DACs the converter should support bit depths of: 18, 20, 24 - I suggest to support 16 as well

Cheers,
Zsolt
Attached Images
File Type: png PCM63 timing.png (32.0 KB, 512 views)
File Type: jpg I2StoAD1865converting.jpg (120.6 KB, 490 views)

Last edited by vzs; 13th April 2012 at 09:54 AM.
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Old 13th April 2012, 10:40 AM   #344
vzs is offline vzs  Europe
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Taking into account zinsula's suggestions of delaying LE the stopped clock timings could be could be smtg like that:
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File Type: jpg I2StoAD1865_PCM63converting2.jpg (119.8 KB, 470 views)
File Type: jpg I2StoPCM170Xconverting.jpg (119.0 KB, 379 views)

Last edited by vzs; 13th April 2012 at 10:51 AM.
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Old 13th April 2012, 12:24 PM   #345
zinsula is offline zinsula  Switzerland
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Quote:
Originally Posted by vzs View Post
[...]Until now I kinda misinterpreted the functionality of LE. It must be set high one (AD1865) or two clock cycles (PCM63/1704) before we want to latch data into the DAC[...]
Hi Zsolt

Strange that with AD1865. With AD 1862, there are no requirements of LE relative to the BCK cycles, only timing requirements:
- LE must go high at least 40ns before LE going low again
- last bit (LSB) must have been clocked in at least 60ns before LE going low
- next word (msb) has to be clocked in earliest 15ns after LE going low
- LE must at least stay low for 40ns

As i understand the function of this DAC, there is a shift register which works with BCK and DATA. As soon as all bits are loaded, you have to stop the clock OR go low with LE immediately (IE left justified data).
LE is just there to start the convesrion of all bits. Therefore the above timing requirements makes completely sense.

Edit:
Here you may see that for AD1856, the left channel bit clock is already stopped before loading the data.
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Last edited by zinsula; 13th April 2012 at 12:39 PM.
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Old 13th April 2012, 12:32 PM   #346
zinsula is offline zinsula  Switzerland
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For PCM1702, Datasheet states the following:

Quote:
(5)
IOUT changes on positive going edge of the 4th clock after negative going edge of Latch Enable (LE).
So I believe it needs 4 clocks.

There are so many different requirements, it's kinda difficult to have all OK for all DAC's.
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Old 13th April 2012, 01:03 PM   #347
zinsula is offline zinsula  Switzerland
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Quote:
Originally Posted by zinsula View Post
[...]

Edit:
Here you may see that for AD1856, the left channel bit clock is already stopped before loading the data.

Of course i meant:
Here you may see that for AD1856, the left channel bit clock is already stopped before LE going high.

Sorry for the confusion.
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Old 13th April 2012, 01:16 PM   #348
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Quote:
Originally Posted by zinsula View Post
Strange that with AD1865. With AD 1862, there are no requirements of LE relative to the BCK cycles, only timing requirements:
- LE must go high at least 40ns before LE going low again
- last bit (LSB) must have been clocked in at least 60ns before LE going low
- next word (msb) has to be clocked in earliest 15ns after LE going low
- LE must at least stay low for 40ns

As i understand the function of this DAC, there is a shift register which works with BCK and DATA. As soon as all bits are loaded, you have to stop the clock OR go low with LE immediately (IE left justified data).
LE is just there to start the convesrion of all bits. Therefore the above timing requirements makes completely sense.
You are right that neither AD1862 nor AD1865 has requirements of LE relative to BCK cycles and I admit that extrapolating the required LE timing to clock cycles is confusing and error prone.
After all I think the timing I proposed is still valid for AD1865, PCM63 and PCM1704.

Zsolt
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Old 13th April 2012, 01:23 PM   #349
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Originally Posted by zinsula View Post
Of course i meant:
Here you may see that for AD1856, the left channel bit clock is already stopped before LE going high.

Sorry for the confusion.
I still think there is a confusion in the middle. On figure 2b. I see the "classic" left justified data format where bit clock (CLK) is continuously running thus LE (Latch) should go down together with the LSB data (DATA).
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Old 13th April 2012, 05:57 PM   #350
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Originally Posted by analog_sa View Post
Would it be possible to add 24 bit as well. Please
24 bit AND working with the 1704 would be nice... Could somone build it, please...
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