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Old 12th April 2012, 01:01 PM   #331
vzs is offline vzs  Europe
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Quote:
Originally Posted by regal View Post
Can you share your schematic?
This is the I2S to LSBJ converter I'm using: link
Note to the schematics: the MCK divide by 2 is not needed, you can simply reclock with MCK so only 5 ICs are needed. The data lines for L and R are shared and the word latches are distinct. The actual pcb schematics I used is here: link . I removed the MCK divider from it and added a U-FL connector for the MCK. You could either do this on breadboard or I could send you the gerbers.
As you see I wasn't aware to use high frequency flip-flops for reclocking nor to comply with LVTTL systems. You should use 74HCT ICs, I used 74HC so I had to lower the supply voltage to 4V to have VIH low enough. If you need more info about this schematics/build let's move to the thread where I posted it.
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Old 12th April 2012, 01:23 PM   #332
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Originally Posted by zinsula View Post
I think I'll open a thread, as I have some ideas, but with "traditional" logic.

It would convert from I2S with 32bit frames as this FIFO spits out, to the right justified data the AD1862 and ..65 needs.
AD1862 being different to AD1865 in that it accepts 20bit depth.
Bit lenght could be even switched i think.

The solution i have in my head would not "interrupt" the Word Clock line with logic, nor it would be necessery to reclock it, so to maintain the essential jitter performance as good as it comes out from FIFO.
I took the main idea from Eric Juaneda's decoder: link and slightly modified it.
This can convert a 64bit I2S stereo sample into the preferred bit depth LSBJ format. The reclocking of Word Clock is mandatory to have everything in sync but will not degrade at all because it is done with the MCK from FIFO (as on FIFO's clock module).
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Old 12th April 2012, 03:28 PM   #333
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Quote:
Originally Posted by vzs View Post
I have to listen to it more relaxed for a couple of days to have a better impression.
My suggestion for a listening test using the FIFO, whether you are 100% isolated from the (jittery) source or not:

a) use original CD an music with many room information (Jazz, Blues etc)

b) rip the a) CD and burn them on a (carbon) CD-R using 1:1 speed or even using master mode speed (old Yamaha F1 do this) or paint the CD-R edges green with a permanent marker.

if you identify any differences then ooooh.... dear.... it will not be your last tweak O

Cheers

Hp
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Old 12th April 2012, 04:00 PM   #334
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Originally Posted by HpW View Post
My suggestion for a listening test using the FIFO, whether you are 100% isolated from the (jittery) source or not:

a) use original CD an music with many room information (Jazz, Blues etc)

b) rip the a) CD and burn them on a (carbon) CD-R using 1:1 speed or even using master mode speed (old Yamaha F1 do this) or paint the CD-R edges green with a permanent marker.

if you identify any differences then ooooh.... dear.... it will not be your last tweak O

Cheers

Hp
(carbon) CD-Rs are my favorite, they sound almost like vinyl without the harsh digital sound of el-cheapo bulk CDs. I already tried different colors for carbon CD-R edges but for me orange is the non-plus-ultra. It gives a warm, tubey sound, without being harsh, also spacial information is so good that I can not only hear Norah Jones in front of me but I can fuzzily see her.
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Old 12th April 2012, 08:40 PM   #335
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Default CREEK CD50 MK2 CD PLAYER

Fifo buffer was used in the Cane Creek CD50 MK2 with great results.

https://docs.google.com/viewer?url=h...cd50review.pdf
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Old 13th April 2012, 12:50 AM   #336
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Quote:
Originally Posted by vzs View Post
Hi Ian,
Finally I integrated the FIFO into my NOS DAC system and did a quick listening session.
With the generic clock, default clock module and simple 74HCxx based circuitry in the AD1865 converter it's already better then before, but I'm too biased now I have to listen to it more relaxed for a couple of days to have a better impression. I have in plans to change the clocks and build Demian's regulator for them.

Do you recommend connecting a better regulator to the whole clock module or just to the clocks separately? - as you did while testing with the batteries.
If feeding the whole clock module from a reg like Demain's or Salas' will the on-board ADP151 regulators degrade/increase this ultra-low noise floor?


It would be really nice to swap eight ICs with one CPLD/FPGA - four reclocking flip-flops would be needed anyway.
I would be happy to buy such a pre-programmed IC or even a whole kit project. Do you have in plans to start such a converter project or should I better invest in a bunch shift-registers ?
Very good progress. What I'm suggesting is:

1. Get a really nice lock first, it will make you distinguishing the good power supply.

2. Based on my own experience, feeding batteries into the reg and feeding them directly into the oscillator (without reg) dosen't make much difference. However, feeding a ac based regulated dc supply into the reg was making big difference. You already know what I mean .

The most significant problem is, the rectifiers are actually working at switching mode. Your could even receiving that rectifying noise from a short wave radio! Fast recovery diodes are better, but still can't eliminate those rectifying noise 100%. That noise comes with very high bandwidth extending to couple of GHz, no regulator could supress them very well. Multi-order CLC filters are working, but you have to design them with carefull to catch up with batteries.

Having more fun with your project

Regard
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Old 13th April 2012, 01:25 AM   #337
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Quote:
Originally Posted by zinsula View Post
I think I'll open a thread, as I have some ideas, but with "traditional" logic.

It would convert from I2S with 32bit frames as this FIFO spits out, to the right justified data the AD1862 and ..65 needs.
AD1862 being different to AD1865 in that it accepts 20bit depth.
Bit lenght could be even switched i think.

The solution i have in my head would not "interrupt" the Word Clock line with logic, nor it would be necessery to reclock it, so to maintain the essential jitter performance as good as it comes out from FIFO.

However, we would need to tap WCK as it serves as a Flag for BCK stopping and directing into the correct channel (L/R).

So we can "oversample" via software, save the Files as eg. 192/20 (or whatever the DAC chip can accept), and play it via USB or S/PDIF. The FIFO will reduce the jitter as good as it gets, AND spit out a single format without having to take into account bit depth or whatever.

TDA1541A would not need any modification of this FIFO output, as it accepts I2S.
Quote:
Originally Posted by vzs View Post
This is the I2S to LSBJ converter I'm using: link
Note to the schematics: the MCK divide by 2 is not needed, you can simply reclock with MCK so only 5 ICs are needed. The data lines for L and R are shared and the word latches are distinct. The actual pcb schematics I used is here: link . I removed the MCK divider from it and added a U-FL connector for the MCK. You could either do this on breadboard or I could send you the gerbers.
As you see I wasn't aware to use high frequency flip-flops for reclocking nor to comply with LVTTL systems. You should use 74HCT ICs, I used 74HC so I had to lower the supply voltage to 4V to have VIH low enough. If you need more info about this schematics/build let's move to the thread where I posted it.
Thank you so much for sharing your ideas. You make things getting more and more interesting. If I did this projcet, I'd like to use a CPLD.

1. It will cover both AD1865(18bit) and AD1862(20bit), as well as PCM63(20bit).
2. Accept I2S signals with sck from 48Fs to 64Fs. left and right justified, maybe.
3. Shifting left and right data into registers at same time and stop clk after doing that to reduce noise further more.
4. Launching left and right channel conversion at same moment to eliminate the phase difference.
5. All signals will be re-clocked by a high-speed low jitter flip-flop with the FIFO master clock before feeding into DAC.
6. Support DAC working at both stereo and mone mode.

I attched the possible timing waveform (take AD1865 for example). Please let me know if there is any problem.

Cheers,

Ian
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File Type: jpg I2StoAD1865converting.jpg (87.0 KB, 536 views)
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Last edited by iancanada; 13th April 2012 at 01:29 AM.
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Old 13th April 2012, 05:47 AM   #338
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Does anyone here connect the FIFO, Dual Clock and S/PDIF with a Buffalo DAC III?
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Old 13th April 2012, 06:25 AM   #339
HpW is offline HpW  Switzerland
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Well,

Quote:
Originally Posted by merlin2069er View Post
Fifo buffer was used in the Cane Creek CD50 MK2 with great results.

https://docs.google.com/viewer?url=h...cd50review.pdf
as mentioned in #333. Listening tests with different jittery CD/CD-R's you will get the trough! While Marl Levinson used this technique years ago and they did not prove using the mentioned bench test.

While I did also more then 15 years ago a PIC controlled crystal DACVCO (almost a free running) and had finally the same issue and then my project went ^^^....

Currently I deal with my setup Wadia 851 CD with Glas Link, modified Wadia 27 DAC, modified Cary SL-100 monoblocks & Magnepan 3.6 and have the big differences (some more some less) between those CD/CD-R's and even playing the same wave file trough a RME Babyface & optical link. As soon times comes trough I would like to measure (using D-Jitter signals or else...) and see what happens... that's why I build my measurement SW

Hp
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Old 13th April 2012, 07:20 AM   #340
zinsula is offline zinsula  Switzerland
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Quote:
Originally Posted by iancanada View Post
[...]

I attched the possible timing waveform (take AD1865 for example). Please let me know if there is any problem.[...]
Sounds good Ian!

One suggestion: Please delay LL and LR (Latch Enable) going down one or more clocks after loading the data and stopping clock. So everything is quiet when the Chip does the conversion.

The other thing being, you cannot use this scheme with PCM1702/1704, as they need the Bit Clock running constantly. They do the conversion 2 or four bits after LE going down.
Not a problem for those using the AD or PCM63 converters, this is just to point that out.
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