Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 33 - diyAudio
Go Back   Home > Forums > Source & Line > Digital Line Level

Digital Line Level DACs, Digital Crossovers, Equalizers, etc.

Please consider donating to help us continue to serve you.

Ads on/off / Custom Title / More PMs / More album space / Advanced printing & mass image saving
Reply
 
Thread Tools Search this Thread
Old 10th April 2012, 04:03 PM   #321
zinsula is offline zinsula  Switzerland
diyAudio Member
 
zinsula's Avatar
 
Join Date: Mar 2004
Hi Ian, maybe this question has been answered already, but nevertheless....

1. Is the FIFO relying on word clock = 64x bit clock, i.e. 32bit for each channel? Or does it clock out WS the same as is clocked in, independently of length of the word clock (i.e. from 16 to 32 bits).
Please note, I'm not talking about how many bits the data word has....

2. If, for example, I'd like to stop the bit clock after 20 bits of data until the next WS transition, would, at the exit of the FIFO, the bit clock stop too?

Thank you for your support!
Tino
__________________
If you can't trust your ears, then CLICK HERE
  Reply With Quote
Old 11th April 2012, 12:41 AM   #322
diyAudio Member
 
iancanada's Avatar
 
Join Date: Dec 2009
Location: Toronto
Quote:
Originally Posted by zinsula View Post
Hi Ian, maybe this question has been answered already, but nevertheless....

1. Is the FIFO relying on word clock = 64x bit clock, i.e. 32bit for each channel? Or does it clock out WS the same as is clocked in, independently of length of the word clock (i.e. from 16 to 32 bits).
Please note, I'm not talking about how many bits the data word has....

2. If, for example, I'd like to stop the bit clock after 20 bits of data until the next WS transition, would, at the exit of the FIFO, the bit clock stop too?

Thank you for your support!
Tino
1. The FIFO output sck will be 64Fs with each channel 32bit no matter how many bits you input for right and left. For example, you can input I2S signal with 16 sck for each channel, but output will still be 32bit 64Fs with the rest LSBs fill in zero.
2. For the FIFO input I2S, you can stop bit clock after 20, the output will play continuoully without any problem. It's FIFO , the output clock has no business with input clock.

It's the nature of I2S protocol. That's why 16bit I2S signal can be played at 24 bit DAC. Please refer to I2S standard which was linked in the end of user's guide, maybe it's more clear than what I said.

Good luck with the KIT
__________________
Ian GBV - I2S to PCM converter board & FIFO KIT
http://www.diyaudio.com/forums/group...ml#post3662743
  Reply With Quote
Old 11th April 2012, 06:38 AM   #323
zinsula is offline zinsula  Switzerland
diyAudio Member
 
zinsula's Avatar
 
Join Date: Mar 2004
You Delta Sigma DAC guys are spoiled

As always, i should have explained why i was asking a question.


Quote:
Originally Posted by iancanada View Post
1. The FIFO output sck will be 64Fs with each channel 32bit no matter how many bits you input for right and left. For example, you can input I2S signal with 16 sck for each channel, but output will still be 32bit 64Fs with the rest LSBs fill in zero.
OK, that answers almost both questions...the output is not just an exact (and "realigned" in time domain) copy of the three input lines, but stuffed with additional bits on the data line (albeit zeros) and corresponding bit clock, up to 32 bits per channel.


Quote:
Originally Posted by iancanada View Post
For the FIFO input I2S, you can stop bit clock after 20, the output will play continuoully without any problem. It's FIFO , the output clock has no business with input clock.
Well, in some cases it's good this way, in some others not...
I have to stop the clock, because the DAC i plan to use accepts right justified data, and it is a 20 bit dac. If i do not stop the clock after the first 20 bits, it will clock in another 12. In case of 16 bit audio, i'll get only silence without stopping the clock.
And i thought to stop the clock before the FIFO, avoiding additional logic after it.

Quote:
Originally Posted by iancanada View Post
It's the nature of I2S protocol. That's why 16bit I2S signal can be played at 24 bit DAC. Please refer to I2S standard which was linked in the end of user's guide, maybe it's more clear than what I said.
I know the I2S protocol....but as i said, you guys with D/S DAC are spoiled.
AD R2R DAC's (eg AD1862) do not follow the I2S protocol, unfortunately.
Look here for a journey into the good old days: http://www.analog.com/static/importe...60163AN207.pdf

With the fifo, I'll delay the word clock 1 BCK before FIFO to align MSB with the word clock, and stop the clock and split left and right data after the FIFO.
As the AD1862 (or AD1865, PCM63 for instance) will trigger conversion based on word clock going negative, word clock jitter performance is to watch for.
But as the needed logic on the word clock line between FIFO and DAC's are only two XOR gates for phase splitting, i think i'll be ok.

Maybe I'll open a separate thread for this.

Thank you anyway
__________________
If you can't trust your ears, then CLICK HERE
  Reply With Quote
Old 11th April 2012, 01:41 PM   #324
diyAudio Member
 
iancanada's Avatar
 
Join Date: Dec 2009
Location: Toronto
Quote:
Originally Posted by zinsula View Post
You Delta Sigma DAC guys are spoiled

As always, i should have explained why i was asking a question.




OK, that answers almost both questions...the output is not just an exact (and "realigned" in time domain) copy of the three input lines, but stuffed with additional bits on the data line (albeit zeros) and corresponding bit clock, up to 32 bits per channel.



Well, in some cases it's good this way, in some others not...
I have to stop the clock, because the DAC i plan to use accepts right justified data, and it is a 20 bit dac. If i do not stop the clock after the first 20 bits, it will clock in another 12. In case of 16 bit audio, i'll get only silence without stopping the clock.
And i thought to stop the clock before the FIFO, avoiding additional logic after it.


I know the I2S protocol....but as i said, you guys with D/S DAC are spoiled.
AD R2R DAC's (eg AD1862) do not follow the I2S protocol, unfortunately.
Look here for a journey into the good old days: http://www.analog.com/static/importe...60163AN207.pdf

With the fifo, I'll delay the word clock 1 BCK before FIFO to align MSB with the word clock, and stop the clock and split left and right data after the FIFO.
As the AD1862 (or AD1865, PCM63 for instance) will trigger conversion based on word clock going negative, word clock jitter performance is to watch for.
But as the needed logic on the word clock line between FIFO and DAC's are only two XOR gates for phase splitting, i think i'll be ok.

Maybe I'll open a separate thread for this.

Thank you anyway
Hi Man,

I suspected your are using AD1865, and now I got the confirm!

Actually, I like the sound of AD1865. I'm listening to it everyday from my PCM-7040 DAT (I connect a S/PDIF FIFO to it ). So,you see, I'm still not 100% be spoiled .

For it doesn't support I2S format, to interface AD18xx DAC with my FIFO, there are two solutions:

1. Design an interface board converting the I2S stream into AD18xx format.
2. Integrating that interface into the FPGA/CPLD on the FIFO board.

I'm looking forward to your new thread to see what kind of help I can provide,

Best regards,
__________________
Ian GBV - I2S to PCM converter board & FIFO KIT
http://www.diyaudio.com/forums/group...ml#post3662743
  Reply With Quote
Old 11th April 2012, 02:07 PM   #325
vzs is offline vzs  Europe
diyAudio Member
 
Join Date: Dec 2005
Location: Cluj-Napoca, Romania
Quote:
Originally Posted by iancanada View Post
For it doesn't support I2S format, to interface AD18xx DAC with my FIFO, there are two solutions:

1. Design an interface board converting the I2S stream into AD18xx format.
2. Integrating that interface into the FPGA/CPLD on the FIFO board.
Being in the AD1865 interface boat I found interesting the proposal of integrating the AD18xx interface into the FPGA but unfortunately it doesn't seems feasible for me. At least one inverter is still needed to differentiate between L/R word selects and the 11.34us delay of the right channel is still there (with 44.1KHz format)
or do you know how to get a "true" AD18xx format out of the FIFO board: 1 frame select, 2 data lines with data aligned as 18bit LSBJ and 1 clock ? I would be interested
  Reply With Quote
Old 11th April 2012, 03:03 PM   #326
zinsula is offline zinsula  Switzerland
diyAudio Member
 
zinsula's Avatar
 
Join Date: Mar 2004
Quote:
Originally Posted by vzs View Post
[...]and the 11.34us delay of the right channel is still there (with 44.1KHz format)[...]
Well that is not really something i care much about. Corresponds to about 4mm sound travel, and is constant over full bandwith.


As the AD1862 (and 1865, or BB PCM63) do convert the data based on word clock (or Latch Enable LE), it is important to have low jitter on these lines.
Stopping BCK does indeed also help to allow conversion without any other line "polluting" the DAC internals and ground.
I believe, the PMD100 digital filter did something along these lines too.

BCK would be important for PCM1702/1704, as they start conversion 2 or 4 bit clocks after LE going down.
__________________
If you can't trust your ears, then CLICK HERE
  Reply With Quote
Old 11th April 2012, 11:25 PM   #327
diyAudio Member
 
iancanada's Avatar
 
Join Date: Dec 2009
Location: Toronto
Quote:
Originally Posted by zinsula View Post
Well that is not really something i care much about. Corresponds to about 4mm sound travel, and is constant over full bandwith.


As the AD1862 (and 1865, or BB PCM63) do convert the data based on word clock (or Latch Enable LE), it is important to have low jitter on these lines.
Stopping BCK does indeed also help to allow conversion without any other line "polluting" the DAC internals and ground.
I believe, the PMD100 digital filter did something along these lines too.

BCK would be important for PCM1702/1704, as they start conversion 2 or 4 bit clocks after LE going down.
Quote:
Originally Posted by vzs View Post
Being in the AD1865 interface boat I found interesting the proposal of integrating the AD18xx interface into the FPGA but unfortunately it doesn't seems feasible for me. At least one inverter is still needed to differentiate between L/R word selects and the 11.34us delay of the right channel is still there (with 44.1KHz format)
or do you know how to get a "true" AD18xx format out of the FIFO board: 1 frame select, 2 data lines with data aligned as 18bit LSBJ and 1 clock ? I would be interested
Hi zinsula, Hi vzs,

Both of you made very good point.

1. Stopping the clock after latching 18/20bit data is a very smart idea. It make sense to reduce the noise floor.

2. Latching left and right data at same LE falling edge is another good idea. At least, it could eliminate the 11.34us phase difference between the two channels.

3. Instead of using mclk, AD1865/2,PCM63 use LE launching the conversion, so, it would be better to re-clock those signals with a hi-speed low jitter flip-flop by a good master clock to maximize the performance.

4. Because of the signals feed to those DACs are totally different from I2S, so the converter board should be stand along from the FIFO board which is following the I2S standard.

That would be an attractive project for FPGA/CPLD based design.
__________________
Ian GBV - I2S to PCM converter board & FIFO KIT
http://www.diyaudio.com/forums/group...ml#post3662743

Last edited by iancanada; 11th April 2012 at 11:29 PM.
  Reply With Quote
Old 12th April 2012, 08:00 AM   #328
vzs is offline vzs  Europe
diyAudio Member
 
Join Date: Dec 2005
Location: Cluj-Napoca, Romania
Hi Ian,
Finally I integrated the FIFO into my NOS DAC system and did a quick listening session.
With the generic clock, default clock module and simple 74HCxx based circuitry in the AD1865 converter it's already better then before, but I'm too biased now I have to listen to it more relaxed for a couple of days to have a better impression. I have in plans to change the clocks and build Demian's regulator for them.

Do you recommend connecting a better regulator to the whole clock module or just to the clocks separately? - as you did while testing with the batteries.
If feeding the whole clock module from a reg like Demain's or Salas' will the on-board ADP151 regulators degrade/increase this ultra-low noise floor?

Quote:
Originally Posted by iancanada View Post
4. Because of the signals feed to those DACs are totally different from I2S, so the converter board should be stand along from the FIFO board which is following the I2S standard.

That would be an attractive project for FPGA/CPLD based design.
It would be really nice to swap eight ICs with one CPLD/FPGA - four reclocking flip-flops would be needed anyway.
I would be happy to buy such a pre-programmed IC or even a whole kit project. Do you have in plans to start such a converter project or should I better invest in a bunch shift-registers ?

Last edited by vzs; 12th April 2012 at 08:23 AM. Reason: spelling correction
  Reply With Quote
Old 12th April 2012, 12:09 PM   #329
regal is offline regal  United States
diyAudio Member
 
Join Date: Jan 2004
Location: MD
Quote:
Originally Posted by vzs View Post
Hi Ian,
Finally I integrated the FIFO into my NOS DAC system and did a quick listening session.
With the generic clock, default clock module and simple 74HCxx based circuitry in the AD1865 converter it's already better then before, but I'm too biased now I have to listen to it more relaxed for a couple of days to have a better impression. I have in plans to change the clocks and build Demian's regulator for them.

Do you recommend connecting a better regulator to the whole clock module or just to the clocks separately? - as you did while testing with the batteries.
If feeding the whole clock module from a reg like Demain's or Salas' will the on-board ADP151 regulators degrade/increase this ultra-low noise floor?


It would be really nice to swap eight ICs with one CPLD/FPGA - four reclocking flip-flops would be needed anyway.
I would be happy to buy such a pre-programmed IC or even a whole kit project. Do you have in plans to start such a converter project or should I better invest in a bunch shift-registers ?
Can you share your schematic? I can't decide where to use my fifo eith with a pair of AD1862's or a TDA1541. For the AD1862 I was going to send the fifo i2s to a PMD100 and forget NOS due to the complexity of format conversion. A CPLD that did the conversion and L/R split would be ideal for the NOS crowd we have been left out in the cold with asynch usb and basically any means to have a master clock at the DAC short of as you say 8+ IC's which tends to make one question if we gain much by forgoing the oversampling filter. A CPLD/FPGA for NOS'ers would be a godsend.
  Reply With Quote
Old 12th April 2012, 12:37 PM   #330
zinsula is offline zinsula  Switzerland
diyAudio Member
 
zinsula's Avatar
 
Join Date: Mar 2004
I think I'll open a thread, as I have some ideas, but with "traditional" logic.

It would convert from I2S with 32bit frames as this FIFO spits out, to the right justified data the AD1862 and ..65 needs.
AD1862 being different to AD1865 in that it accepts 20bit depth.
Bit lenght could be even switched i think.

The solution i have in my head would not "interrupt" the Word Clock line with logic, nor it would be necessery to reclock it, so to maintain the essential jitter performance as good as it comes out from FIFO.

However, we would need to tap WCK as it serves as a Flag for BCK stopping and directing into the correct channel (L/R).

So we can "oversample" via software, save the Files as eg. 192/20 (or whatever the DAC chip can accept), and play it via USB or S/PDIF. The FIFO will reduce the jitter as good as it gets, AND spit out a single format without having to take into account bit depth or whatever.

TDA1541A would not need any modification of this FIFO output, as it accepts I2S.
__________________
If you can't trust your ears, then CLICK HERE
  Reply With Quote

Reply


Hide this!Advertise here!
Thread Tools Search this Thread
Search this Thread:

Advanced Search

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are Off
Pingbacks are Off
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
XMOS-based Asynchronous USB to I2S interface Lorien Digital Source 2185 22nd October 2014 02:04 PM
exaU2I - Multi-Channel Asynchronous USB to I2S Interface exa065 exaDevices 1357 3rd March 2014 08:51 PM
DAC chip selection + I2S jitter questions drwho9437 Digital Line Level 2 26th July 2010 12:50 PM
Simple FIFO to I2S CPLD, for MCU players / reclocking KOON3876 Digital Line Level 21 19th September 2008 04:00 PM
asynchronous reclocking and low jitter clocks ash_dac Digital Source 3 8th February 2005 09:22 AM


New To Site? Need Help?

All times are GMT. The time now is 08:50 AM.


vBulletin Optimisation provided by vB Optimise (Pro) - vBulletin Mods & Addons Copyright © 2014 DragonByte Technologies Ltd.
Copyright 1999-2014 diyAudio

Content Relevant URLs by vBSEO 3.3.2