Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 302 - diyAudio
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Old 21st October 2013, 04:36 AM   #3011
AR2 is offline AR2  United States
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Quote:
Originally Posted by hochopeper View Post
Hi AR2
Also, while you're talking about multichannel it always helps to give Ian a gentle reminder that he's toying with ideas for a multichannel FIFO :P
Chris
Chris,
It seems like you have a habit giving a good advice, and I have a tendency to follow it, haha. I feel bad "gently reminding" Ian on any project because he has been over productive in his achievements that materialize for our pleasure. Just look at his GBs, man half of diyaudio got his board. Another one like Ian is Acko in his steady production of outstanding ideas.

As for Titan, it fancy U.FL and pin headers in the output. Titan has two clocks, in my case Crystek 957 45.xxx and 49.xxx There is also MCK out. I am unclear if you suggested to use Titan as master clock and just distribute that clock to DAC boards? I do have a separate, clock buffer board from Acko. That might be the idea, but I have to figure out how it will work like that. That clock distribution board has XO (Crystek 957 100 MHz) on it, power supply for the clock and fast buffer with 4 outs through U.FLs. XO could be removed and in its place U.FL so I guess that is where I could plug MCK from Titan and disytribute to DACs? But I think that is not really ideal solution. The reason I was thinking about Si570 is because it already has inverted outs, and it makes DAC master and Titan slave. In addition, I have two of those. :-)

I was also thinking about Acko's turbo clock and do not know if that will do what I need since that is stand alone board.
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Old 21st October 2013, 04:38 AM   #3012
AR2 is offline AR2  United States
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Originally Posted by iancanada View Post
Hi AR2,

It's great you back to the thread. How are you doing?

I'm thinking about your questions now and will get back to you very soon.

Have a good night.

Ian
Thank you Ian! I am fine, very happy to have a time again for diy. Hope you are doing well?

My best

Vladimir
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Old 21st October 2013, 05:31 AM   #3013
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AR2 I think the simplest way would be to do a small PCB for clock buffering for u.fl input of MCLK, BCLK, FSCLK signals and providing w.fl outputs to suit the ackoDAC boards. The PotatoSemi 74G38072A seems a nice fit for that. I've got a few of the 4 way version (38074A) of that chip at home waiting for a few other things to come together so I can give them a run.

It would depend on what the output of the Titan provides (analogue parameters of the gates) to determine if you need to buffer the BCLK and LRCLK because they're going to have a much longer duty cycle than the MCLK, with some damping you may be able to get away without a buffer on those two. Parallel clock lines is an exercise in minimising stray capacitance mostly but using coax u.fl and w.fl you're getting a good start on that.

A board with a buffer adapter to split the signals for the two DAC boards would probably be the neatest solution. As much as I'm hesitant to add yet another PCB to the mix (I'm personally trying to keep my new projects away from becoming the diy 'beast of a thousand PCBs') I think I'd rather that than the complexity of adding the Si570.

That's my vote on the solution at least, I'll keep an ear to the ground to see if Ian thinks up something smarter than I've got in mind


BTW, my 'gentle reminder' to Ian is just a friendly ribbing and intended to be with a giant cheeky grin on my face and I hope Ian knows I mean no malice by anything like that. His productivity is prodigious! You're right, he's contributed far more of his time, knowledge and gear than most in his relatively short time at DIYA. I'm not shy about telling people that Ian's project has inspired me to try some of my own designing. I'm a nerd so I actually have enjoyed the learning side of this thread as much as the great sound that I've got from my FIFO powered headphone system


Chris
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Old 21st October 2013, 05:49 AM   #3014
AR2 is offline AR2  United States
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It does make a lots of sense. I will hold on Ian to hear what is his opinion. I also posted question about Turbo Clock on Acko's thread. I like the simple approach, and yes, buffered distribution board is something, I believe many would like. In the meantime, I will send you a LightHarmonics data sheet if you do not have one, to give you idea what it has and how is configured. If you would need picture or any measurement, please let me know.

Thanks and appreciate your help very much!
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Old 21st October 2013, 09:29 AM   #3015
Marek is offline Marek  Poland
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moved form group buy thread:

Quote:
Originally Posted by andrea_mori View Post
any re-clocking circuit adds jitter itself.
(...)
Andrea
Quote:
Originally Posted by Marek View Post
Its not true. Synchronous reclocking used by Ian greatly lowers jitter of I2S signals. Ofcourse I2S after synchronous reclocking isn't jitter free - it has jitter of XO acumulated with jitter generated by FF, thats why Ian uses POTATO Ghz FF which has one of the lowest induced jitter available.
Other thing is asynchronous reclocking with clock not related to any of I2S signals - it adds jitter but it can be compared to dithering used in computer graphics or in audio and depending of used reclocking frequency can bring some relative improvement (output jitter character not related to source jitter, to content of binary audio signal etc)

Marek
Quote:
Originally Posted by andrea_mori View Post
Synchronous reclocking used by Ian is essential since the FPGA adds some jitter to the I2S signal, regardless from the quality of the original signal.
POTATO's FF has a propagation delay around 2ns, so maybe a low jitter but not jitter free.
IMHO, when the BCK is also the MCLK the DAC can be fed directly with I2S signal, without any additional stage that still injects jitter, since the internal logic of the 1541A operates at MCLK frequency.

Andrea

Yes, in FIFO input jitter is totally rejected and output jitter comes only from FPGA architecture + incoming MCLK jitter (reletively low).

POTATO's FF constant propagation delay has nothing to do with jitter. Sorry, but talking about propagation delay in context of jitter is a mistake. For example clock signal can be delayed 10ns and have jitter of 1ps.

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Old 21st October 2013, 12:09 PM   #3016
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Quote:
Originally Posted by Marek View Post
moved form group buy thread:








Yes, in FIFO input jitter is totally rejected and output jitter comes only from FPGA architecture + incoming MCLK jitter (reletively low).

POTATO's FF constant propagation delay has nothing to do with jitter. Sorry, but talking about propagation delay in context of jitter is a mistake. For example clock signal can be delayed 10ns and have jitter of 1ps.

Marek
Of course, I said "maybe low jitter" and not "2ns propagation delay then low jitter" (maybe fast settling), but I said also "not jitter free" (i cannot find anything about jitter in PO74G74A datasheet).

BTW, the debate is about the sense to introduce more stages when probably they are not needed, or, if you want, about the performance of the internal logic of the 1541A when it runs at MCLK against external solutions.

Andrea
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Old 22nd October 2013, 03:09 AM   #3017
tofurky is offline tofurky  United States
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Default tps7a4700 capacitor recommendation

i'm planning on using one of ian's TPA7A4700 regulators configured for 5v to supply the AVDD (analog) pin of my ak4396 dac.

currently the dac is configured like MC7809->AMS1117-5->AVDD.
MC7809 has 100nF+10uF at its output
AMS1117-5 has 47uF at its output
AVDD has 10uF by the input.

i've attached an image showing what my plans are to fit the TPA7A4700 regulator in place of the AMS1117-5. i will lift the input pin of the AMS1117 to disable it, and remove the 47uF capacitor to provide vout and gnd connections for the TPA7A4700 pcb. vin will come from a jumper wire attached to the output of the MC7809 (using the "accessible" input pad of another regulator; see red trace).

my first question is: any issues with running it with a long vin jumper wire like that?

second: looking at the provided schematic for the TPA7A4700 pcb, there are optional oscon input and 1uF film (i think?) capacitors.
which of these, if any, would benefit this application? and if 1uF is already a good value for the output, what capacitance would be ideal for the input? is oscon still a good choice for this application given that it's for the analog vin of the ak4396, or should i look for something like a nichicon KA/KZ?

here's some ideas so far:
output:
BC Vishay MKT370 1uf/63v
input:
Sanyo OSCON SEPC 470uF/16v
Nichicon Muse KZ 100uF/25v

thanks,
-matt
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Old 22nd October 2013, 03:25 AM   #3018
mikela is offline mikela  United States
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Quote:
Originally Posted by hochopeper View Post
Also, while you're talking about multichannel it always helps to give Ian a gentle reminder that he's toying with ideas for a multichannel FIFO :P

Chris
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Old 22nd October 2013, 06:03 PM   #3019
tofurky is offline tofurky  United States
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Quote:
Originally Posted by tofurky View Post
currently the dac is configured like MC7809->AMS1117-5->AVDD.
MC7809 has 100nF+10uF at its output
AMS1117-5 has 47uF at its output
AVDD has 10uF by the input.
correction, by default the AMS1117-5 is fed from a (nearby) MC7812, not the pictured MC7809. i would like to jumper the TPS7A4700 vin over to the MC7809 though to take the load off of the MC7812, because the MC7812 is also used for the opamps in the output stage.
thanks,
-matt
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Old 24th October 2013, 04:36 AM   #3020
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Quote:
Originally Posted by AR2 View Post
Hello Ian and guys,

It has been awhile for me since I posted here. Ian, I just recently installed my Si570 clock board with no problems. There is slight problem when at 384 KHz, some noise comes out when no signal applied, but than disappears. It also need ssome warm up time. Up to 192 KHz all is cool. But that is not my question. With my previous project where I use FIFO board, I failed to achieve what I originally wanted - all digital crossover. For various reasons I ended up with digital front end and analog crossover.

Now I am starting a new project where I will try to do what I wanted originally, all digital crossover. After very helpful conversation I had with Hochopeper I decided for my crossover to be Titan - LightHarmonics USB to I2S multichannel board and two Acko DACs ESS 9012 boards. Obviously I cannot use FIFO here since there are two DACs, but I was thinking in using Si570 board as master clock for clocking all of the boards in synchronized operation. Titan has possibility of being in the slave mode and Si570 board has as far as I understand 3 MCK outs - two inverted and terminated with 50 ohm and one unterminated and I guess non inverted. I am unclear in the following:
Do I bring to connectors of Si570 World Clock, Bit Clock and one Data signal, and rout all out MCK signals?

Or maybe I do not connect any signals to Si570 board and just pull MCK signals out to each board? Coming out of the Titan Board, World Clock and Bit Clock signals are all the same for all 4 channels, the only difference is data.

Now, there is also thing that Si570 board will not change frequency automatically when in stand alone mode. Does that also stand if world clock and Bit clock signals are delivered to it, so if signal changes its sampling rate Si570 will do it automatically as well?

Thank you
Hi Vladimir,

I’m sorry for getting back too late. I was tied up with the GBV. Fortunately my wife lands a hand.

I could be wrong, but if I understood your project with correct, my multi-channel/DSD FIFO would be your perfect solution. It will have 14 channels at I2S mode and 8 channels at DSD mode. I already finished the DDR memory controller, the FIFO management and other basic modules, but I have to design the DSD receiver, transmitter, zero signal detector and other related sections. I’m working on an Altera FPGA verification KIT now, will transfer to my own PCB after passing all the simulation and real test. The only problem is I don’t know when I will finish this project. I won’t want it slow down your project.

Si570 clock board works in this way: together with the FIFO board, they work as a close loop frequency control. So, there is a Mega8 on the Si570 board to perform the management. In order to avoid introducing any noise into clock board, Mega8 works in a very special way: sleeping mode with only a couple of uA power consumption. When FIFO found can’t lock to an input Fs, it will wake up the Mega8, Meaga8 will figure out what frequency needs to set by pick up the Fs measurement result from FIFO via SPI bus. Then, the Si570 driver will set a new frequency, and at same time xFs will also be sent into FIFO. Mega8 will go into deep sleep mode again after doing the above jobs. It seems a bit tricky, but there is no any secret code, if hochopeper found a bit difficult to control the si570 board, it's all because of the special working mode. You need a real time software to communicate with it at the window time.

Si570 board can work standalone as a master clock for sure, but I just cannot figure out how to switch between frequencies without the supporting of FIFO.

The three I2S input signals on the clock board are just for re-clocking, they are equal, so you can feed any signals rather than limited to any specified one. All three MCLK output are inverted to the flip-flop clock which can be accessed form one pin of R28.

Or, might be, think about if there is any possible we make two stereo FIFO working in parallel mode, one for master and the other is slave…. Please let me know your idea.

Some time, I need switch gear for a while. I was trying to fix iMac at board/BGA level last month. Now we have three iMac27s, form 2009 to 2011 models, one for myself, one for my son and other one for my mother in law. All of them are fixed from “as parts no working iMac”. I think I should open a thread on iFixit now.

Thanks guys, I’ll focus on the multi-channel/dsd project the next, it would be really exciting project.

Regards,

Ian
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