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Old 26th July 2011, 10:54 PM   #21
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Quote:
Originally Posted by qusp View Post
Hey Ian, yeah sorry i should have linked it and i forgot the dot in w.fl, its that type, but the one i'm using is a touch more upmarket, its made by hirose and comes available with double shielded mini coax cables, it looks to be the same, or at least similar connection standard as the one you linked, but its a bit pricier and does seem, or at least looks higher quality. its also described as ultra low coax smd, so perhaps its lower profile.
Hi Qusp, Thank you for the update. I sourced them by those info. They are from Hirose and there are W.LF(2*2) and U.LF(3*3) two series. like: Digi-Key - H9161CT-ND (Manufacturer - U.FL-R-SMT(10)) and Digi-Key - H9173CT-ND (Manufacturer - W.FL-R-SMT-1(10)) . I will try to get some samples and to see if I could use them. BTW, very professional baord desing, as well as the smart idea about the digital audio interconnection. Regards, Ian
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Old 26th July 2011, 11:19 PM   #22
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Do you detect "silences" between songs and allow the fifo to go to half full again (remove/add some silence)?

But indeed interesting. Seems easier than trying to build an extra pll
Hi GuidoB, Thank you for interesting. You are smart guy. You know the secret! Totally agree with you. Yes, in this design, the smart FIFO strategy has already been included inside the FPGA. That means, for the continuous music signal, the FIFO overflow time is 1486s(under those conditions), but for the normal music playback, the fifo depth could be adjusted during the silence between songs to keep it at certain level. So, for most of the cases, FIFO will not overflow and you will never feel the existence of the FIFO except the delay. Cheers, Ian

Last edited by iancanada; 26th July 2011 at 11:23 PM.
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Old 30th July 2011, 12:18 AM   #23
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Default The FIFO playing test

Finally, it starts playing and it sounds correct. The FIFO concept is working!

I2S FIFO configuration:
I just have a spare AD1955 DAC board. It has onboard I2S input and output ports which could be very easy to interfaced with my FIFO. Those ports were designed originally for the DSP, but in its normal setup, the I2S bus was bypassed by jumpers. Both input and output ports of the I2S on the FIFO are the 7pin connectors, 4 of 7 pins are GND between the signals to reduce the crosstalk.
The DAC has a coaxial SPDIF input, the DIR chip is BB DIR9001.
The FIFO was driven directly by an external OSC (11.2896MHz for 44.1KHz with MCLK 256*Fs), as well as the MCLK input of the AD1955. And now you can see this OSC become the secondary clock of the new clock domain and has nothing to do with the MCLK generated by the DIR9001.
I use batteries to power the OSC and the FIFO. The CYCLON battery is my favorite. Batteries usually come with less noise and much better performance to power the clock related circuits which are very sensitive to the noise from the power supply.

The system setup:
Speakers: B&W Nautilus 804;
Power Amplifier: PASS LABS ALEPH 5 (DIY, clone);
Pre-Amplifier: PASS LABS ALEPH P1.7 (DIY, clone);
Source: KRELL KPS 20i/L CD transport & MAGNAVOX CD player

Testing result:
1. It sounds correct, just confirmed the bit perfect test I did before;
2. When I switched the SPDIF cable from KRELL KPS 20i/L CD transport to MAGNAVOX CD player, it sounds same no any audible difference, the FIFO concept is working!
3. When I bypassed I2S signals on the AD1955 board, and let them come directly from DIR9001, it sounds different;
4. The delay was around 0.5 to 1s and not that obviously. It just feels like a bit slow on the button of the CD player. I could hardly notice it in most of the cases;
5. FIFO didn’t overflow during the entire test.

Since the FIFO board is working, now we already have a platform to taste the different clock oscillators. So, the next step I’m gonna do some test connected to the clock.

Enjoy my basement. Have a nice weekend. Ian
Attached Images
File Type: jpg I2SFIFOandDAC.JPG (473.4 KB, 3307 views)
File Type: jpg B&W804Speakers.JPG (290.0 KB, 3151 views)
File Type: jpg Krell20iCDtransport.JPG (410.0 KB, 2951 views)

Last edited by iancanada; 30th July 2011 at 12:24 AM.
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Old 31st July 2011, 03:06 AM   #24
qusp is offline qusp  Australia
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looking good Ian, i too prefer batteries for clock and also use them for powering the analogue sections of the dac (3v3 for AVCC L/R and 1v2 for analogue reference) but I use LiFeP04 by A123. what battery chemistry are the Cyclon?

beautiful speakers btw, the B&W are some of the best i have ever heard. Thats a pretty serious Disk spinner you have there, is that face actually made of stone haha, or just a finish on the alloy. it looks like it opens up Star Trek style.


I cant take credit for the Dac layout in the picture, Acko did that (thus Ackodac) i did however push for using the micro BNC for all inputs on the upgraded Teflon board (having owned the previous version as well), which was to be a limited edition when we got the first small run of 6 boards (4 for me, 2 each for me and vy friend); but turned out so well it became standard.

I have used them in a few of my own builds since then, but that one wasnt me.

this project of yours us quite interesting for my spdif sources, I cant see it making an improvement on my usb->i2s setup, which might actually complicate the use of your board with my main dac unless i run it from the same master clock, which i guess is the idea, muxing might be difficult though.

regardless i do have another dac in the workshop rig it will work well with, so when you finish testing and do a board run let me know, i'll pop my head in from time to time.
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Old 31st July 2011, 11:11 AM   #25
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Good work Ian,

Great to see it working as well as it is.....

Fran
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Old 31st July 2011, 12:57 PM   #26
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right i checked them out, cyclon are SLA? mate if you like batteries, i really recommend you try out LiFeP04, imo it leaves all other battery chemistries in the dust. output impedance is very very low, noise is lower than SLA, charges in a jiffy and even just the smallish size 3v3 (nominal) 2300mah ANR26650m1 is capable of 70A continuous output with burst rate up to 120A!! output impedance is less than 10mOhms and the nominal voltage is extremely convenient for digital circuits.

i'm quite amazed at the rate of your progress also!!
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Old 2nd August 2011, 01:29 AM   #27
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Glad to know that someone has the similar interest. Nice board!

I started a similar project in the summer of '09. The basic idea was very similar, only that the I/O peripherals have more varieties. Instead of I2S I/O, I also added S/PDIF I/O (via BNC and XLR), isolated USB input and an LVDS I2S input over HDMI cable compatible with the PS Audio spec. I was able to get a few 1MB (8Mbit) SRAM (those are not cheap if you buy new) for a slightly deeper FIFO depth. I used an old FPGA that is large enough for the logic. The actual FIFO depth is determined by measuring the clock frequency difference between the incoming signal and the local reference clock, such that the minimum amount of FIFO is used to reduce latency. In addition to PCM, the logic also supports DSD64 (in a 176.4KHz/16bit PCM container when transported via S/PDIF or I2S).

Soon I found that the FPGA I picked does not have the ideal clock resources I need, and the logic resource is not enough for future expansion. I had to abandon the board that I spent quite some time to layout, fab and assemble, let alone the cost of the parts. The core logic is not complicated, but I want to add more 'fun' to it.

Then I turned to a low-cost FPGA development board, the Digilent NEXYS. It has almost all I need for a digital audio front-end: a 500k Gate FPGA with DCM and multipliers, 8MB(64Mbit) PSRAM (DRAM+controller that works like an SRAM), 32Mbit NOR flash and a USB 2.0 high-speed device controller. The I/Os are more than enough for the audio application. A character LCD interface with the switches and push buttons make a reasonably good UI.

A more elaborate plan was laid out: turn the all-hardware design into an embedded system. A PicoBlaze CPU was added for user control and status indication on the LCD. It opens a can of worms and I quickly realized that the software is the most time-consuming part of this project. In this new platform, I was also able to add S/PDIF receiver and transmitter logic such that I'm no longer limited by the features of the off-the-shelf S/PDIF Tx/Rx ICs. A firmware was developed for the USB 2.0 device controller for USB audio class device that is capable of Hi-res.

Again, it wasn't long before I realized that the old architecture has become the bottleneck of this system. I can do a lot more on this platform: A 32-bit CPU with enough performance to run software FLAC decoding, an SDIO interface that enables solid-state player function, oversampling and decimation filters using the FPGA multipliers, etc, etc.

Unfortunately, while I was going full-steam with this project, I was interrupted by a business trip, followed by a serious personal incident that almost knocked out all my interest in this project.

I guess that's it. If you have plenty of time and ambition, think big, or soon you'll find yourself being trapped in a small PLD, a small PCB, or an architecture that is just enough to do what you thought of at the beginning.

It wasn't a bad idea to sell a few boards while you make new ones, though. That'll encourage you to move forward but could also slow you down with the support responsibilities. It depends. Good luck!

(Attached is the 'discontinued' board, only one was made)
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Old 2nd August 2011, 04:45 PM   #28
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I would be interested in just the fifo function, not a complete set. Maybe also a programmed fpga to integrate on my own pcb later on.

Bit of a lego construction; add an spdif receiver on one side (have a small pcb available) and a filter/dac/clock on the other side.

But then, i could also continue with the pll. Or just buy something nice

I'm wondering about live concerts, in case there are no silences inbetween the songs. What happens if the fifo runs full or empty ??
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Old 2nd August 2011, 05:52 PM   #29
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The problem is the RAM size. Large SRAM is not cheap and not easy to come by. Or you can go DRAM with a slightly more complex memory controller. Since the RAM size needed is the function of supported sample rate, bit depth and clock frequency difference, one can calculate how much RAM is enough.
500ppm is a good, practical starting point, but I would opt for 1000ppm, which is IEC60958 standard for S/PDIF streams. In order to support a stereo 192KHz/32bit PCM stream at 1000ppm clock frequency error without FIFO overflow over a continuous 1.5 hour playback (gap-less), you'll need about 8MB (64Mbit) of memory.
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Old 2nd August 2011, 05:55 PM   #30
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Today CAS become more and more popular, considering a DAC may not just or even no more for CD playback, and more and more 24/88.1 or higher rate files could buy or share online, I will suggest do more test for 24/88.1 or higher rate playback, plus maybe even upgrade the FIFO support up to 384KHz, since 32/384 USB DAC or USB-I2S interface starting appear in the market already.
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