Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

[qusp]

nope, Tom would be much more obvious if he was flaming me, he just happens to spend his days creating proofs with strings. of course now he mentions it ive seen/read this many times, but had math text/brain fail and dont mind admitting it when i do, doesnt make me feel stupid

and wow who woulda thunk it, 2 people among ~20million collide across teh interwebz...amazin.....

[iancanada]

Originally Posted by zinsula

Thank you Ian. This could well be an option, but if using an external clock, the "comfortable" automatic clock switching is lost.
Primarily, I'd plan to connect the FIFO to a multi format DVD player, which puts out both the 44.1 and the 48kHz - Family of sample rates.
But I'll take one...

Hi zinsula,

Design a clock board for my fifo with automatically Fs switching function is easy. As I mentioned before, the fifo board is working at slave mode, the clock board is the master. The default MCK is 256Fs, so just desigen a clock board, output 11.2896MHz if I2S is 44.1K and 12.2880Mhz if I2S is 48K(your clock board should know which Fs it is). Anything else will be dealt with at background by fifo fpga/cpld. If MCK frequency is not match the I2S, the output of the fifo will be silenced automatically until right frequency is being fed. Just hope it works for your idea.

Good luck zinsula,

Ian

[zinsula]

Thanks Ian. As I am at a remarkable loss when it comes to program something, I would have some troubles to let the clock board know which clock it has to select. So I'm playing safe and ordered the dual clock board too.....

[qusp]

the regulator circuits on the board are actually pretty trick, particularly given the high quality HPF and LPF through the use of newish 4 pole capacitor/inductor networks

[nattonrice]

Originally Posted by qusp

nope, Tom would be much more obvious if he was flaming me

So very true

I do enjoy proofs involving strings!

[qusp]

even typing that sounded clumsy


sneaky bastard...

[vzs]

Lastly I will add my 18bit LSBJ converter board after the reclock kit and have some more questions before doing the pcb:
1. As the SCK output has to drive 11 gates on my converter board do I need a buffer like 74ACT125 or can the reclocked FIFO output source that many gates?
2. Can you tell me the Farnell code of the 7-pin PH 2.0mm connector + double-ended PH cable you are using as I couldn't find them.
3. I'm trying out the single clock board and plan to use it with 44.1KHz based stream. Can I use a 22.5792MHz clock (512*Fs) or do I have to stick with a 11.2896MHz one?

Thanks.
Zsolt

[iancanada]

Originally Posted by vzs

Lastly I will add my 18bit LSBJ converter board after the reclock kit and have some more questions before doing the pcb:
1. As the SCK output has to drive 11 gates on my converter board do I need a buffer like 74ACT125 or can the reclocked FIFO output source that many gates?
2. Can you tell me the Farnell code of the 7-pin PH 2.0mm connector + double-ended PH cable you are using as I couldn't find them.
3. I'm trying out the single clock board and plan to use it with 44.1KHz based stream. Can I use a 22.5792MHz clock (512*Fs) or do I have to stick with a 11.2896MHz one?

Thanks.
Zsolt

Hi Zsolt,
1.The max output current of the I2S signals from the clock board is LVTTL +-20mA, but 11 gates are too much for keeping low jitter performance. Suggest useing low jitter dedicate clock fanout buffer driving them. The one on the Dual XO clock board is one of the good choice, only 18fs additive jitter. Don't let AD1865 share clock driver with other load.

2. 7PIN PH2.0 Digikey P/N
455-1739-1-ND SMT
455-1709-ND through hole

U.FL cable
H11555-ND

U.FL socket
H11891CT-ND

3. The default master clock of the FIFO is 256Fs except other setting by the external mcu. So if you using the single clock board, you have to stick with 11.2896MHz for 44.1K. Changing the default to 512Fs is easy, I can re-program it for you if you want before defivery so that you can use the 22.5792M clk. The only thing is I don't have enought time doing the test for that special version.

Regards,

[glt]

Originally Posted by iancanada

3. The default master clock of the FIFO is 256Fs except other setting by the external mcu. ...
Regards,

Is there a s/w interface to the FPGA?

[iancanada]

Originally Posted by glt

Is there a s/w interface to the FPGA?

Yes, FIFO integrated a 32bit SPI.