Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 283 - diyAudio
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Old 13th June 2013, 02:29 PM   #2821
qusp is offline qusp  Australia
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Whats the point of an enable pin being there if all you have to do is turn it off? i'm well aware that it 'works' having done it myself for years. but how exactly does leaving it off remove the output from being in parallel? this is definitely a last 1% solution, but as I see it, its a real phenomena.

thats the whole point of having a tristate clock/buffer, otherwise the output of the buffer is left hanging there in parallel with the input clock, rather than being put into a hi-Z state. not applying power does not correct this, the buffer is still there. the effect is bound to be minimal, but its there and I believe it was of some significance in Ians testing

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Old 13th June 2013, 03:03 PM   #2822
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There is no enable pin. It simply presents a high impedance node, and has no effect.
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Old 13th June 2013, 03:04 PM   #2823
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i'm sure it allows faster cycling/reaction than switching it on and off, probably starts up quicker, but is that really it?

no enable pin? what? whats the E/D (Enable/Disable) then? yes, exactly, the E/D pin puts it into a hi-Z state so it does nothing ...

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Old 13th June 2013, 03:08 PM   #2824
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Quote:
Originally Posted by qusp View Post
i'm sure it allows faster cycling/reaction than switching it on and off, probably starts up quicker, but is that really it?
I don't understand your question.
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Old 13th June 2013, 03:09 PM   #2825
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ahh sorry Brian, you are still using a variant of the 950 yes? the 957 have an enable pin. not sure what impact that has on the internal structure though.

what I meant was, in a situation where you might have 2 clocks sharing a line, say with dual clock operation here in audio; if you simply used power cycling to turn them on or off, then there is a good chance it would take longer to switch on/off vs waking a disabled clock from a sleep state. would probably be less predictable too

I was providing counterpoint, another reason for an enable pin being there if switching it off had the same effect. I do wonder if the fact it doesnt have one, really means its effectively not there if not on. Are the internal structures that different with 950 vs 957? to me, if its not to do with the waking up bit, I dont know another explanation for them putting an enable pin on the clocks that are similar to 950, but designed for situations where they might share a clock line. (as they are only available in audio clock speeds for 44.1/48x)

Last edited by qusp; 13th June 2013 at 03:21 PM.
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Old 13th June 2013, 08:04 PM   #2826
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Another issue that I work, with the DSP of the Ref 7.1şÍ§Ó*µ响 , what are the optimal frequencies of clocks that I have to put on the FIFO card clocks?
Reponse of Kingwa (Designer Audio GD)

The DSP1 jitter control have not contact with the source clock frequency.
Usually high frequency is better.
Kingwa

comments?

Last edited by clsidxxl; 13th June 2013 at 08:16 PM.
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Old 13th June 2013, 08:34 PM   #2827
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Quote:
Originally Posted by qusp View Post
ahh sorry Brian, you are still using a variant of the 950 yes? the 957 have an enable pin. not sure what impact that has on the internal structure though.

what I meant was, in a situation where you might have 2 clocks sharing a line, say with dual clock operation here in audio; if you simply used power cycling to turn them on or off, then there is a good chance it would take longer to switch on/off vs waking a disabled clock from a sleep state. would probably be less predictable too

I was providing counterpoint, another reason for an enable pin being there if switching it off had the same effect. I do wonder if the fact it doesnt have one, really means its effectively not there if not on. Are the internal structures that different with 950 vs 957? to me, if its not to do with the waking up bit, I dont know another explanation for them putting an enable pin on the clocks that are similar to 950, but designed for situations where they might share a clock line. (as they are only available in audio clock speeds for 44.1/48x)
My understanding from talking with Crystek is that the enable pin has both advantages: ability to keep the oscillator powered and stabilized, and to revert the output to high impedance (I have not confirmed this second point, but it would make sense).
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Old 14th June 2013, 12:42 AM   #2828
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From the CCHD-957 data sheet:

It also features a “Standby Function”, that is, when placed in disable mode, the internal oscillator is completely shut down in addition to its output buffer being placed in Tri-State.
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Old 14th June 2013, 11:23 AM   #2829
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Quote:
My understanding from talking with Crystek is that the enable pin has both advantages: ability to keep the oscillator powered and stabilized, and to revert the output to high impedance (I have not confirmed this second point, but it would make sense).
Quote:
From the CCHD-957 data sheet:

It also features a “Standby Function”, that is, when placed in disable mode, the internal oscillator is completely shut down in addition to its output buffer being placed in Tri-State.
Lol. So, opposite of what I said.
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Old 16th June 2013, 09:24 PM   #2830
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Hi guys,

can somebody please enlighten me - should my setup be able to play above 192kHz?

Amanero - FIFO KIT & Si570 - sync to Buff II

I'm only getting loud crackling noise at 352 and 384kHZ. Not sure if I've overseen something or if there's a natural limitation in this setting.

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