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Old 4th April 2013, 12:27 AM   #2641
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Quote:
Originally Posted by iancanada View Post
The source selecting was done by FPGA hardware, the last setting can not be saved and re-called. It's not difficult to design a panel board to take care of the control and display. Last setting can be re-called on next power up. A small MCU would be good for this kind of application, or you can use an Arduino.
I think this MCU+display could be made more universal and allow control over DAC also (for those using FIFO with a DAC with SPI/I2C interface). I have emailed you ...


Chris
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Old 4th April 2013, 12:34 AM   #2642
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Quote:
Originally Posted by hochopeper View Post
I think this MCU+display could be made more universal and allow control over DAC also (for those using FIFO with a DAC with SPI/I2C interface). I have emailed you ...


Chris
That's a great idea.

Ian
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Old 4th April 2013, 04:56 AM   #2643
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Quote:
Originally Posted by iancanada View Post
Good to know that, Oliver

Do you want to run the dual xo from 3.3V battery direct? You have to remove the on board low noise LDO. But I don't think it's problem for you. Let me know if you need a picture of the set up.

The source selecting was done by FPGA hardware, the last setting can not be saved and re-called. It's not difficult to design a panel board to take care of the control and display. Last setting can be re-called on next power up. A small MCU would be good for this kind of application, or you can use an Arduino.

I2S back door...? Do you need fixing it?

Regards,

Ian
Hi Ian,

i would like to run it direct with my Salas SSLV. If its only the one onboard LDO and no other parts, than i could handle it.
But i saw that more guys are interested in the direct 3.3V mod., so a photo will be helpful.

My I2S backdoor on the S/PDIF runs perfect. Its only the source selecting i was talking about

Cheers,
Oliver
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Old 4th April 2013, 01:17 PM   #2644
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Default Passive/Active Hybrid Battery Monitor Suggestions

I have been thinking of ways to get the battery monitor to monitor and shut down to prevent over discharge conditions damaging batteries, without defeating isolation during listening times.

I am not sure if this should be part of a 'FIFO controller' uController design mentioned above, or a revision to the battery monitor board, or a mix of the two.


The FIFO J13 connector provides a signal that indicates period of silence. I am not sure of the latency of this signal, how quickly is this status changed Ian?

During period of silence, could a relay be toggled such that an active battery monitor chip (or a simple comparator) is able to check the battery? Perhaps an optically isolated solid state relay since this relay will see far more operations than any of the other relays in this system.

I have in mind that it could work as follows:

- silent status received, toggle relay to switch in the battery monitor circuit
- silent status goes to a 555 timer delay to ensure that the battery monitor has time to properly evaluate the battery low status, eliminate transient conditions
- then an AND or NAND on the delayed silent signal and the comparator/battery monitor chip's output should provide a signal that can be used to disconnect the battery

I haven't thought through a proper lockout timer process yet. May need to provide an output of the 'battery low shutdown' condition for use by other connected equipment (other battery monitor boards, input to MCU for status reporting of each battery supply etc).

The above adds the following components to the current design:
- active monitor/comparator
- current 555 timer for inrush current can become a dual 555 timer SOIC16 instead of SOIC8
- single and gate chip - could be SOT package
- passive components for setting trigger levels and delay timer.

This shouldn't result in unmanageable levels of additional complexity compared to the existing schematic and can be an additional 'optional' portion on a revised PCB.


I know some of this was discussed in non-specific posts a while back, I've tried to come up with a cohesive solution that tackles it in a relatively simple way without making it unnecessarily complex.


Cheers,
Chris
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Old 4th April 2013, 06:20 PM   #2645
bisesik is offline bisesik  Kazakhstan
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Hi, Ian. Could you be so kind to reply to me on my email (have sended 29.04) Thanks.
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Old 5th April 2013, 01:32 AM   #2646
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Quote:
Originally Posted by bisesik View Post
Hi, Ian. Could you be so kind to reply to me on my email (have sended 29.04) Thanks.
Didn't see your email. Can you send it again? Thanks.

Ian
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Old 5th April 2013, 01:50 AM   #2647
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Quote:
Originally Posted by hochopeper View Post
I have been thinking of ways to get the battery monitor to monitor and shut down to prevent over discharge conditions damaging batteries, without defeating isolation during listening times.

I am not sure if this should be part of a 'FIFO controller' uController design mentioned above, or a revision to the battery monitor board, or a mix of the two.


The FIFO J13 connector provides a signal that indicates period of silence. I am not sure of the latency of this signal, how quickly is this status changed Ian?

During period of silence, could a relay be toggled such that an active battery monitor chip (or a simple comparator) is able to check the battery? Perhaps an optically isolated solid state relay since this relay will see far more operations than any of the other relays in this system.

I have in mind that it could work as follows:

- silent status received, toggle relay to switch in the battery monitor circuit
- silent status goes to a 555 timer delay to ensure that the battery monitor has time to properly evaluate the battery low status, eliminate transient conditions
- then an AND or NAND on the delayed silent signal and the comparator/battery monitor chip's output should provide a signal that can be used to disconnect the battery

I haven't thought through a proper lockout timer process yet. May need to provide an output of the 'battery low shutdown' condition for use by other connected equipment (other battery monitor boards, input to MCU for status reporting of each battery supply etc).

The above adds the following components to the current design:
- active monitor/comparator
- current 555 timer for inrush current can become a dual 555 timer SOIC16 instead of SOIC8
- single and gate chip - could be SOT package
- passive components for setting trigger levels and delay timer.

This shouldn't result in unmanageable levels of additional complexity compared to the existing schematic and can be an additional 'optional' portion on a revised PCB.


I know some of this was discussed in non-specific posts a while back, I've tried to come up with a cohesive solution that tackles it in a relatively simple way without making it unnecessarily complex.


Cheers,
Chris
Hi, Chris

The silence signal will only happen when Fs is switching or FIFO is lost lock. So, it usually takes long time.

I suggest use a passive voltage meter monitoring the battery. Any active component will generate noise. But we have to figure out how to protect battery from over discharge beside shut down the power manually when battery is low.

I'll use a bigger battery pack together with passive monitoring gauge and make sure battery being charged all the time while system is off.

Let me know for any good idea.

Regards,

Ian
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Old 5th April 2013, 01:57 AM   #2648
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Quote:
Originally Posted by iancanada View Post
Hi, Chris

The silence signal will only happen when Fs is switching or FIFO is lost lock. So, it usually takes long time.

I suggest use a passive voltage meter monitoring the battery. Any active component will generate noise. But we have to figure out how to protect battery from over discharge beside shut down the power manually when battery is low.

I'll use a bigger battery pack together with passive monitoring gauge and make sure battery being charged all the time while system is off.

Let me know for any good idea.

Regards,

Ian
Ahhh okay, I was hoping it was an indication of extended period of silence in the i2s stream, which I was hoping might happen often enough for our purpose. I was wrong though. Fs switch and unlock don't happen anywhere near often enough for our needs as you say.


Back to the drawing board for new/more ideas.


Chris
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Old 5th April 2013, 02:06 AM   #2649
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Quote:
Originally Posted by hochopeper View Post
Ahhh okay, I was hoping it was an indication of extended period of silence in the i2s stream, which I was hoping might happen often enough for our purpose. I was wrong though. Fs switch and unlock don't happen anywhere near often enough for our needs as you say.


Back to the drawing board for new/more ideas.


Chris
Actually my FPGA logic has that I2S zero detecting signal inside which might be the one you want, I just didn't assign a pin for it .

Ian
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Old 5th April 2013, 07:39 AM   #2650
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Originally Posted by iancanada View Post
Actually my FPGA logic has that I2S zero detecting signal inside which might be the one you want, I just didn't assign a pin for it .

Ian
That sounds like exactly what I want
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