Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 26 - diyAudio
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Old 24th February 2012, 12:26 PM   #251
qusp is offline qusp  Australia
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thanks!! hey how do you reckon the fifo will go with the upcoming possible DSD over USB standard? it requires that the data is not resampled, but buffered is ok I would think
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Old 24th February 2012, 01:34 PM   #252
vzs is offline vzs  Europe
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Hey Ian,
I have some question regarding interfacing your board with my system.
As my AD1865 DAC needs a 18bit LSBJ stream I'm using a simple converter board with a shifter logic like this: link to convert 32bit I2S to 18bit LSBJ. Basically data is shifted with 13 clocks.

- As I don't want to use double output reclocking -first with your board then with mine - I thought I could create a small data-shifter board and plug it between the FIFO board and single XO clock board, therefore the clock board would receive an LSBJ stream with data shifted. Am I right that the reclock part does not care about what it reclocks, so this approach can work?

- How does the FIFO board receives the master clock from the single XO clock board?
- What is the reclock frequency: 128Fs or 256Fs?

Thanks!
Zsolt

Last edited by vzs; 24th February 2012 at 01:36 PM. Reason: corrections
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Old 25th February 2012, 02:00 AM   #253
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Quote:
Originally Posted by vzs View Post
Hey Ian,
I have some question regarding interfacing your board with my system.
As my AD1865 DAC needs a 18bit LSBJ stream I'm using a simple converter board with a shifter logic like this: link to convert 32bit I2S to 18bit LSBJ. Basically data is shifted with 13 clocks.

- As I don't want to use double output reclocking -first with your board then with mine - I thought I could create a small data-shifter board and plug it between the FIFO board and single XO clock board, therefore the clock board would receive an LSBJ stream with data shifted. Am I right that the reclock part does not care about what it reclocks, so this approach can work?

- How does the FIFO board receives the master clock from the single XO clock board?
- What is the reclock frequency: 128Fs or 256Fs?

Thanks!
Zsolt
Hi Zsolt,
I like AD1865. My PCM7040 sounds perfect!
I analyzed your schematics, the answer is yes. You could insert your converter boare between fifo and single clock board. The default reclock frequency is 256Fs for the single clock board. FIFO receive the master clock from the FFC/FPC interface cable. You are right, my reclock circuit reclock signals by the master clock no matter what they are. Logiclly, there is no difference reclock at 128Fs or 256Fs. However, reclock by master clock directly will have less jitter.
Have a nice weekend.
Ian

Last edited by iancanada; 25th February 2012 at 02:10 AM.
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Old 25th February 2012, 08:41 AM   #254
regal is offline regal  United States
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Quote:
Originally Posted by iancanada View Post
Hi Zsolt,
I like AD1865. My PCM7040 sounds perfect!
I analyzed your schematics, the answer is yes. You could insert your converter boare between fifo and single clock board. The default reclock frequency is 256Fs for the single clock board. FIFO receive the master clock from the FFC/FPC interface cable. You are right, my reclock circuit reclock signals by the master clock no matter what they are. Logiclly, there is no difference reclock at 128Fs or 256Fs. However, reclock by master clock directly will have less jitter.
Have a nice weekend.
Ian
So you do mean this unit outputs true Phillips 16+16 I2S (if it is input) as opposed to the difficult 32x32bit wordlength format that has recently come about with most of the usb implementations ?
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Old 25th February 2012, 05:15 PM   #255
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Quote:
Originally Posted by regal View Post
So you do mean this unit outputs true Phillips 16+16 I2S (if it is input) as opposed to the difficult 32x32bit wordlength format that has recently come about with most of the usb implementations ?
Hi regal,
This I2S FIFO accepts true 16bit to 32bit I2S input range (actually sck input from 32fs to 64fs). Internally, the FIFO memory is true 32bit processing. Output sck is 64fs (I2S standard, same as most DIRs). No problem if you feed true 32bit I2S, bit perfect confirmed.
Have a nice weekend.
Ian
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Old 25th February 2012, 07:28 PM   #256
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Salas low volt shunt Reg ! better then this ......
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Old 25th February 2012, 10:57 PM   #257
1audio is offline 1audio  United States
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Can you defend your claim about the salas regulator? What use case? Please contribute more details.

Sent from my T-Mobile G2 using Tapatalk
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Old 25th February 2012, 11:22 PM   #258
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defend what ??

just use search ....
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Old 25th February 2012, 11:39 PM   #259
1audio is offline 1audio  United States
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"Salas low volt shunt Reg ! better then this ......"

Not constructive or useful. How is it better? The noise floor is higher. . .
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Old 25th February 2012, 11:53 PM   #260
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"The noise floor is higher"
Damian sorry if is not sufficient good ,but as DIY is well supported with guide /pcb/GB
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