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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
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Old 2nd March 2013, 12:03 PM   #2521
MisterRogers is offline MisterRogers  United States
Can you say Audio?
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Join Date: Aug 2011
Location: Aurora, Colorado
Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
I believe as Ian has noted re: capacitors/Si570, much of what we're hearing (at this level) are component choices. Amazing really. That's my subjective sense; I have no means of measuring the jitter of each clock board. But I am sonically sensitive to the effects of jitter. That tells me these two are very close, with the dual clock board being very slightly better. When I supply the Si570 via battery, I expect to close that (very small) gap.
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Old 2nd March 2013, 02:14 PM   #2522
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by regal View Post
either permutation is so superior to anything our ears have ever heard with regard to jitter performance it just amazes me that you are hearing differences. I mean at this level, jitter should be completely out of the question. Very odd. Makes me think oscillation/intererfance or some other rf phenomenom is occuring.
Hi regal,

Yes, that's very interesting. I might be wrong, But I think jitter is very similar to FM modulation. MCLK is the carry frequency. Even we got same jitter level from different clock, as if the same amplitude of the modulating signal, but the modulating signal itself may different, for example, music and news are different, even different music.

We are more focus on the jitter numbers. But few people is talking about the characteristics or properties of jitter itself. I believe that really making difference.

Have a nice weekend.

Ian
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Old 2nd March 2013, 02:24 PM   #2523
qusp is offline qusp  Australia
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but isnt it just like 2 stupidly low amounts of wow/flutter?
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Old 2nd March 2013, 02:47 PM   #2524
MisterRogers is offline MisterRogers  United States
Can you say Audio?
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Yes, and THAT is pretty awesome :-)
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Old 3rd March 2013, 12:39 AM   #2525
makumba1966 is offline makumba1966  Poland
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After a long day listening I came to the conclusion that I dont like MLCC caps at the TPS output reg. They give some artifacts to sound. So just replaced 4x10uF MLCC with 10x1 uF/63 film caps. They does not fit on the board ofc, but I very like changes in sound. Midrange and highs are clear and sweet now, huge soundstage, nothing annoys me so far. The best setup for me since got fifo kit.
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Old 3rd March 2013, 07:10 AM   #2526
TNT is offline TNT  Sweden
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Picture and make of caps would be interesting.

/
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Old 3rd March 2013, 10:45 AM   #2527
Blitz is offline Blitz
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Quote:
Originally Posted by MisterRogers View Post
I believe as Ian has noted re: capacitors/Si570, much of what we're hearing (at this level) are component choices. Amazing really. That's my subjective sense; I have no means of measuring the jitter of each clock board. But I am sonically sensitive to the effects of jitter. That tells me these two are very close, with the dual clock board being very slightly better. When I supply the Si570 via battery, I expect to close that (very small) gap.
After installing the fifo, I figured that component changes not only around the clock and the fifo is much more audible, but everywhere, as well in the i/v conversion and tube output stage. The fifo brought me a huge step forward to understand where in my setup are the remaining mistakes....the impression of realismn, transparency and attitudes which I knew only from big, heavy turntables before.
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Old 3rd March 2013, 06:39 PM   #2528
sernikus is offline sernikus
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Hi , i`ve got problem (?) - with BIIISE in synchronous mode +FIFO,isolator,Si_XO board output level (analog) is much lower . In asynchronous mode everything is OK.... the sound in synchro mode is rather "thin" , it lacks "body" . anybody else ?
I suspect BIII SE - it looks like this : Buffalo2-Sabre32 DAC MEGA Test | H i F i D U I N O (1 test result) ...
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Old 3rd March 2013, 09:09 PM   #2529
makumba1966 is offline makumba1966  Poland
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It's fascinating how Si board is sensitive to power regs In my last setup I am using single Kemet polymer cap 100u/16v and it's best option so far. While testing TPS board i want build "Salas style" local shunt. Initial sims are promising. Iam using Kemet caps models.
Attached Images
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File Type: jpg noise.jpg (607.4 KB, 432 views)
File Type: jpg PSRR.jpg (671.3 KB, 422 views)
File Type: jpg TEMPCO.jpg (522.8 KB, 398 views)
File Type: jpg loopGain.jpg (631.4 KB, 300 views)
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Old 3rd March 2013, 10:13 PM   #2530
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by sernikus View Post
Hi , i`ve got problem (?) - with BIIISE in synchronous mode +FIFO,isolator,Si_XO board output level (analog) is much lower . In asynchronous mode everything is OK....
Are you using the MCU on board TPA Buffalo III SE? How is your power on sequence? Before you turn power of BIIISE on, your synchronous master clock must be supplied to the ES9018 device so that the chip can receive initial register setting commands sent from MCU via internal I2C bus. Otherwise, ES9018 starts with its hardware defaults that lack input redirections.
In the case of Buffalo III, any manual DIP switch change triggered a whole register setting again and that enabled a normal operation.
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