Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

[iancanada]

Originally Posted by karvid

I just started my BIIIse together with the Asynchronous I2S FIFO and a dual Clock board.
When I try 192kHz Music and with the MLCK instead of the BIII onboard 100MHz oscillator the BIII don't get a locked signal. I still havn't changed any of the oscillators included in the dual Clock board kit. (with 44.1kHz Music it works great).

It works perfect it I disconnect MLCK and uses the BIII Clock and only the I2S signal from the dual Clock board.

What could be the problem?

Also do anyone have recommendations on what Clocks to use for best performance out from the dual Clock board?


Thanks
Kenneth

I don't have any problem running my BIII at 192KHz with dual xo clock board at 45.xxx/49.xxx MHz XO, or with Si570 clock board. What is your MCLK frequency for now? For ESS DAC running by an external MCLK for sync mode, MCLK frequency has to be greater then 256*Fs at any time, that's the real limitation.

Regards,

Ian

[Nazar_lv]

Is the following expression correct?
phase jitter RMS = 0.1 x period jitter pp

no

[sernikus]

Originally Posted by Blitz

....Here are my Listening impressions:

With 22/24 Crystek 957:
Very warm sound overall. Colorful, rich mids. You follow the music easily. Very robust representation. Perfect ? Well...even though it improved a lot, no complaints on dynamics or 3d anymore, it still is a bit hazy, like if you have a tin-foil cap in the signal path than a mundorf silber supreme or better.

....

... hmmm strange... in my case (FIFO+buffalo iiise_IVYIII) in synchro mode with
22.x ,24.x crystek`s i hear thin , cold (but spacious with very good stereo but flat dynamic) sound ... in asynchronous mode (100MHz BIIISE) sound is very impressive - rich and full. better than my previous system - dual mono Opus dac with FIFO .... i think 90MHz is minimum/optimum for Buffalo (Sabre) Dac`s...

[andrea_mori]

Just about the clock, this is what I'm going to use in a "dated" system such as a CD transport and a 1541 NOS, reclocking the source.
Phase noise around -135dBc@10hz!

[Bunpei]

Does the "Kphi: 0.249" mean "Phase Jitter = 0.249 [ps RMS]"?

If it does so, its period jitter p-p estimation value according to glt's approximation is 2.5 [ps P-P]!

[iancanada]

Just cooked for GBIV. Let me know for any comment.

Ian

[hochopeper]

Thanks Ian!


I have skim read it just now and noticed two things only:

- Page 5 diagram shows 'isolator board' but the page is dedicated to describing the 'no isolator' connection. I think that diagram should change to 'FIFO board' instead of 'isolator board'.

- Copyright statement at the end of your doc shows 2011, that's soooo two years ago man

Otherwise looks excellent as usual and I'll probably read in more detail tonight some time.


Cheers,
Chris

[qusp]

first official release is V3.1 lol

[iancanada]

Originally Posted by hochopeper

Thanks Ian!


I have skim read it just now and noticed two things only:

- Page 5 diagram shows 'isolator board' but the page is dedicated to describing the 'no isolator' connection. I think that diagram should change to 'FIFO board' instead of 'isolator board'.

- Copyright statement at the end of your doc shows 2011, that's soooo two years ago man

Otherwise looks excellent as usual and I'll probably read in more detail tonight some time.


Cheers,
Chris

Thanks Chris, good eye. Corrected. Please wait my V1.0 for the wiki. I'm busy at production now. So far so good. Hopefully I can post GBIV details by this weekend.

Regards,

Ian

[iancanada]

Originally Posted by qusp

first official release is V3.1 lol

V3.5

Ian