Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 233 - diyAudio
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Old 2nd February 2013, 02:47 PM   #2321
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Ok...the fifo is now 2 weeks active, so burning in should be complete.

I got from Ed the 44.x and 49.x version of the Crystek 957 with adapter boards ( thanks again, Ed!!!!).

Here are my Listening impressions:

With 22/24 Crystek 957:
Very warm sound overall. Colorful, rich mids. You follow the music easily. Very robust representation. Perfect ? Well...even though it improved a lot, no complaints on dynamics or 3d anymore, it still is a bit hazy, like if you have a tin-foil cap in the signal path than a mundorf silber supreme or better.

With the 44.x/49.x:
Did i complain about lack of transaprency ? Forget anything I said. Unbelievable fast and transparent. It lacks now the warm character a bit(still only fed by Placid hd shunt), but unbelievable resultion (and I have many Hd recordings). Like a highend Mundorf silver cap. Maybe not yet like a duelund with the color richness, but this could as well come from somewhere else in the chain, will figure it out. Clearly we are entering a new level and now I need to figure out other sources of errors made...

The crysteks are running currently without any decoupling caps...any opions on what would be the best ? smd parts like recommended by ian or mkp 1837 or micas ? hf chokes like tent suggests ? Oscons locally addionally ?
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Old 2nd February 2013, 02:56 PM   #2322
qusp is offline qusp  Australia
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none, the crystek have decoupling internally, you will do more harm than good adding more. the optional placement position on the adapter is for other clocks
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Old 2nd February 2013, 05:17 PM   #2323
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Quote:
Originally Posted by glt View Post
My bet is that the output jitter is dominated by the clocking flip-flops... It would be interesting to do the test with the Crystek. Likely Ian already did that :-)
I have yet to see any datasheet having jitter values for flip flops which sort of indicates that jitter is not an important parameter for flip flops...
All flip flops add jitter.
The fun is that running on 3.3 volt may give 40% less added jitter, but the jitter spectrum are different from when running on 5 volt, and the slew rate are lower when running on 3.3 volt.

I do not know yet what the most important parameters are..
There are more than two ways to determine that - but listening and measurement are the obvious ones..
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Old 4th February 2013, 03:42 AM   #2324
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Quote:
Originally Posted by nvduybom View Post
Sorry for interrupting the thread.

I want to use external power for each FiFO block kit, so with DualXO Clock I will remove L11 and with SPDIF I will remove j10 cable . It is right ? .

Thanks you .
For spdif board, yes, you need remove L1 if you run it from independent power supply.

But for dual xo clock board, you have to keep L11 if work with isolator board.

Ian
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Old 6th February 2013, 12:51 AM   #2325
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does anyone have the schematic link to Ian's 3.3v regulator.

got my mouser order with the ldo and I'd like to start soldering it.

thanks in advance.
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Old 6th February 2013, 01:03 AM   #2326
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Quote:
Originally Posted by necplusultra View Post
does anyone have the schematic link to Ian's 3.3v regulator.

got my mouser order with the ldo and I'd like to start soldering it.

thanks in advance.
The link is in the wiki

I created the wiki about a month ago for exactly this reason, to help people dig up the info buried in the long thread - let me know if you think there is things that could be done better in the wiki and I will try to add/change it to make it more usable for everyone. Also remember the wiki is publicly editable I believe so if anyone has something they would like to add, feel free to contribute

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Old 7th February 2013, 05:02 AM   #2327
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Default Si570 Clock Board GB version V3.5(6) Jitter measurement result

Yesterday, I received a finished GB version V3.5 Si570 clock board sample from my SMTA supplier to confirm. The first thing I did was measuring the real jitter performance. I think this part is what you are interested in the most.

Here is what got:

Period jitter RMS: 3.85 ps
Period jitter peak-to-peak: +-12ps
Jitter distribution: Gaussian
Frequency: 98.3097MHz
N = 10,000 cycles
Sampling at 8GS/s
Please see the attached jitter histogram plot for details

Please note, my oscilloscope comes with 2ps RMS jitter floor. If we take other factors into account, such as testing environment and calibration, the total jitter floor could be even bigger. So, if we exclude those numbers, the actual testing result we can figure out is not bad, very close to the period jitter specification from the official datasheet.

Again, measuring jitter in time domain is not the best way to evaluate a clock. Because we can see jitter from statistics only, but the spectrum. The best way is measuring it in frequency domain by a phase noise analyzer.

However, if we get testing results compared, it still tells a lot of secret. Please find the jitter testing result of the generic XO I posted weeks ago, you can see what is the difference in between.

Ian
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File Type: png Si570V3.5Jitter.png (28.8 KB, 595 views)
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Old 7th February 2013, 05:24 AM   #2328
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Thanks Ian, I think that looks great and seems devoid of the spurious noise some expect from such a device.... where is it guys? most seem to forget, or do not know that the clock is generated by an internal crystal.

for a speed of 98MHz I think this is very good, even if we do not consider the additional advantages of this multiple frequency clock. we can set it to be running at the ideal/preferred FS multiple for each sample-rate.
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Old 7th February 2013, 08:33 AM   #2329
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Looks like a good result, even if Ian is right when saying the phase noise should be the best measurement.

BTW, the measurement should be done at 11.2896MHz, to directly compare to the generic XO measurement, and theorically (I repeat theorically) the noise in frequency domain should be better an so I expect improvement in time domain also.

Quote:
Originally Posted by andrea_mori View Post
Is there any post with the generic XO jitter measurement?
If yes, its jitter is around 6ps or lower?
I assume there is no period jitter measurement of the generic XO (stand-alone, not in the clock board), that could be very useful for to understand where the jitter come from.
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Old 7th February 2013, 09:37 AM   #2330
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Ian, those number look impressive. I did install yesterday the 45.X and 49.X Crystecs to the dual XO and the sound did improve a lot over the standard Xtals.
Next step is to feed the Buffalo with the clock signal from the dual XO with Crystecs.
Question for me is now if the SIC board would be a better choice or if the difference would be rather marginal ...
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