Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 23 - diyAudio
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Old 26th January 2012, 01:16 AM   #221
regal is offline regal  United States
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Originally Posted by qusp View Post
with rice though, you are really supposed to submerge the phone in it, there is not enough rice in china to submerge all of my electronic parts hehe.

hey Regal, i found i had some epsom here, ive baked it, went totally opaque white, which seems logical, but when its absorbed its full of water, does it turn back to clear? just some indication of it doing its job would be cool.

sorry for the OT Ian
yea it will get clumpy/clearer when it absobs the water, but it won't turn back into crystals.
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Old 26th January 2012, 01:51 AM   #222
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Hi Ian,
great project. A couple of questions.
What is the reason you choose to use three PCBs instead of one?
Even if someone doesn't need the SPDIF input, e.g. they want to use USB, the savings on PCB, interconnects etc. are probably in the range of the cost of the SPDIF section anyhow?

In your experience, what is the best performance in terms of jitter that can be achieved using an integrated (single chip or DSP e.g. ADI) ASRC vs your very nice design?
Thanks SunShade, very good questions.

Iím an audiophile, I need more performance, more flexibility, more combination and more try, so I designed this modularized FIFO KIT. However, if I design similar project for consuming market, it would be an all-in-one PCB and could run plug-and-play, just as you mentioned, thatís reasonable.

Actually the FIFO board could work independently from the other two PCB without any problem if you are happy with it. Clock board is just for upgrading the clock performance, while the S/PDIF board is just for expanding DIR and DIT functions.

Later on, Iíll design couple of new clock boards by integrating with different kind of clock solutions. For example, Si570, remarkable low jitter performance (-112db/100Hz, -150db/10MHz) and sounds wonderful, but it need a software based driver to run. Without this upgradeable clock board configuration, we even donít have chance to play with it.

I2S FIFO is kind of straightforward solution to deal with jitter problem. It just uses a new low jitter clock to replace the old one and do not change anything on the I2S data. The principle is very clear, everybody could understand. ASRC is totally the different story. It uses DSP calculating power to up-sample the input I2S data. AD1896 is a very special case of ASRCs. It employed Ďrate estimatorí to get more accurate up-sampling processing which makes it coming with better jitter attenuation than other ASRC chips. Personally, Iím very interested in it. If I get time, Iíd like give it a try to see which one is better.

Have a good nightJ. Ian
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Old 26th January 2012, 12:21 PM   #223
zinsula is offline zinsula  Switzerland
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[...]The statement above does not disagree with my post. but i would like you to show me a regulator that is effective enough at these high frequencies to not leave all of the heavy lifting to the decoupling caps. Salas himself and those in the thread when i asked about this, brought this up WRT the BJT version. i also stated that low noise is still important and asked how the reg you linked compares to the 9uV LDOs. so where exactly do you disagree?

when i find a regulator with better noise performance over the range of interest (and particularly down in the low frequency 'jitter band') than A123 batteries i'll consider it[...]
Regarding noise, Demians regulator he posted on this thread is magnitudes better than any LDO regulator. Let's look at the ADP151 which is coincidentally specified having 9ĶV output noise.
You may look at Figure 23 of this Datasheet. 1/f knee is >10kHz!! Noise is somewhere 20nV/rtHz.
Also, the CFP transistors are very fast, I would think even faster than a LDO, if you are concerned about high frequency. But very high frequencies have to be adressed with capacitors anyway.

Also, Werner Ogiers wrote a nice article about regulator and battery noise here. Page 4 may interest you.

This is a really interesting project, and jitter performance of the I2S signals can be very very good and depending to a great deal from the clock. That's why I believe that substituting the LDO regs with something like Demian's reg is almost mandatory, if you want to get out the most from a good clock and from this FIFO buffer achitecture.
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Old 26th January 2012, 12:41 PM   #224
zinsula is offline zinsula  Switzerland
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Originally Posted by iancanada View Post
[...]I2S FIFO is kind of straightforward solution to deal with jitter problem. It just uses a new low jitter clock to replace the old one and do not change anything on the I2S data. The principle is very clear, everybody could understand. ASRC is totally the different story. It uses DSP calculating power to up-sample the input I2S data. AD1896 is a very special case of ASRCs. It employed Ďrate estimatorí to get more accurate up-sampling processing which makes it coming with better jitter attenuation than other ASRC chips. Personally, Iím very interested in it. If I get time, Iíd like give it a try to see which one is better.
I'd put some money on your FIFO compared to an ASRC, being it TI, AD or whatever.
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Old 26th January 2012, 01:27 PM   #225
qusp is offline qusp  Australia
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I would think even faster than a LDO, if you are concerned about high frequency. But very high frequencies have to be adressed with capacitors anyway.
just as i said in the first post you replied to, i made it pretty clear i thought very high transient speed was not of huge importance

Quote:
Also, Werner Ogiers wrote a nice article about regulator and battery noise here. Page 4 may interest you
this decade old article is of no relevance to todays lithium cells, read it years ago.

as for the rest, i'm really not interested in talking about it, i posted my caveats regarding my post, mentioned i saved Demian's schematic to try along with other things, but you still want to argue? why is that? can we please just get on with talking about the actual subject at hand? you, just as i are free to use whatever clock and power supply you wish; you will never please everyone

@ Ian:

on the other hand i'm dead keen to try out the Si570 DSPLL, which pwns any other clock ive seen i think and simplifies psu design and layout (as long as good RF technique is used for decoupling) due to only needing 1 clock, thanks for the tip Ian!! it has its own internal regulators and PSRR so large i would challenge you to make any meaningful difference past a competently designed IC reg or battery to supply it.

Last edited by qusp; 26th January 2012 at 01:40 PM.
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Old 26th January 2012, 01:42 PM   #226
zinsula is offline zinsula  Switzerland
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Why do you think I'm arguing with you?

I only say that an LDO is by far worse at LF than eg Demian's circuit and that this is detrimental for clock performance.

And I thought that you may be interested in reading the article. No need to feel attacked.

Please go forward with whatever you find important.
Ciao.
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Old 27th January 2012, 07:29 AM   #227
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Ian

Waiting for the GB, such a great job !!!
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Old 27th January 2012, 04:45 PM   #228
1audio is offline 1audio  United States
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Default Si570 + Regulator stuff

The SI570 looks really interesting. However you need to learn how to read datasheets to see the reality. The phase noise numbers and jitter numbers are from a 112 MHz measurement. There is nothing for the range we care about. Also there are no plots. The jitter numbers are more meaningful and the most important for us might be the period jitter of 2 pS rms and 14 pS P-P. DDS solutions usually have spurious outputs and often they are close to the carrier. In some applications they may not matter and they are not usually mentioned when discussing phase noise. Also there is an actual floor below which improving jitter/phase noise will make no difference in a digital system.

If the device is good enough it suggests a simpler solution that the full buffer here- just use it as a PLL locked reclocker following the input frequency. The device has a very wide adjustment +/- 3500 ppm and a source outside of that range would be broken. Taking the basic clock rate info from the line receiver and few latches + some smarts in an fpga + a classic PLL could make a very good reclocking solution. It takes 10 mS to switch to a different frequency so a single Si571 could do the job. Two, programmed at 22.5792 MHz and 24.576 MHz would make it easy and eliminate the need for the reprogramming of the chip. It would need two nominal frequencies selected by the input receiver and a good type 2 PLL to lock quickly and reject short term variations.

As I pointed out elsewhere there is no universal perfect regulator. You will need to make some tradeoffs to get the best solution for a specific application. The circuit I cooked up was targeted specifically at oscillators and getting maximum isolation from the external supplies with low noise. While it seems to work well in other applications its not necessarily the best option if the load is dynamic.

Any amplifier circuit is effectively inductive at its output (the gain falls with frequency so the output Z increases with frequency). As such the output cap becomes more important with frequency.

Making a bypass that is nonresonant and has enough current reserve up to the highest frequency of interest is a challenge and will be a different challenge for each specific application. Every component and trace is an LRC network and most change with voltage and current. Ideally you would measure at the critical pins of the controlled device with a vector network analyzer to see what its impedance is doing across the useful range. This is far from practical. At least think about the problem as a network, not a magic cap.

For the crystal oscillator the current doesn't change ever (unless something is wrong), it is voltage sensitive so voltage needs to be stable and noise free and the ripple current is at the output frequency so its a simple problem. The rest of the digital circuitry in a digital audio device is a much different case.
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Old 28th January 2012, 12:06 AM   #229
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Also there is an actual floor below which improving jitter/phase noise will make no difference in a digital system.
Agree. The best clock is the sampling clock. However, even you use same clock, you couldn't duplicate each phase exactlly the same. Just think about what clock was using by a studio for recording? Even we use the perfact clock for playback, the sampling jitter is still there, impossible to get rid of, that would be meaningless(except the computer based music, which was generated by software without sampling).

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DDS solutions usually have spurious outputs and often they are close to the carrier. In some applications they may not matter and they are not usually mentioned when discussing phase noise.
Si570 is XO based DPLL, not DDS. And Si571 comes with bigger jitter than Si570 (20dB greater on phase noise), I suspect that phase noise was intrduced by the control voltage and the internal ADC.

Ian
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Old 28th January 2012, 12:32 AM   #230
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The bigger jitter makes sense with the large voltage control range.

The real floor of a digital system comes from the digital process. Below a certain jitter number the end value of a sample won't change. Its limited by the resolution (number of bits) of the system. Subdivide the sample rate by the number of increments and that is where the floor in time lives. There are other details that suggest lower jitter is better but at some point it cannot be resolved.
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