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Old 24th January 2013, 09:08 AM   #2231
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Quote:
Originally Posted by qusp View Post
as I understand it there is a lot more than changing clock speeds needed to mod amanero
I was thinking about the cheap Acko isolator relcoker plus the si570 as RFCK. Wouldn't this work?

Quote:
Originally Posted by hochopeper View Post
Si570 doesn't talk i2c ... it needs a UART.
TBH I haven't read Ian's implementation but according to the SI570/571 datasheet (page 17) it would seem to support 2 wire I2C through pins 7 (SDA) and 8 (SDL).
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Old 24th January 2013, 09:29 AM   #2232
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Originally Posted by Jackal29a View Post
I was thinking about the cheap Acko isolator relcoker plus the si570 as RFCK. Wouldn't this work?
This will work as long as you are wanting asynch re-clocking with Acko's board. See below.
Quote:
Originally Posted by Jackal29a View Post
TBH I haven't read Ian's implementation but according to the SI570/571 datasheet (page 17) it would seem to support 2 wire I2C through pins 7 (SDA) and 8 (SDL).
Yes the Si570 chip itself has an i2c interface. Ian has an on board controller that communicates with the Si570 and it is this controller that provides a UART API for external control of the board. This ensures that the external controller gets FIFO events (change of input freq) that would not be possible if he only provided the i2c port.

In your application I think setting a fixed freq and using asynch reclocking would be the best bet.
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Old 24th January 2013, 10:02 AM   #2233
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Quote:
Originally Posted by Popolvár View Post
Ian, great news!

Maybe too late (the frequency groups were here for some time already) but I will try to kindly ask:

Would it be possible to add one more group (or modify the group1) also for older DAC chips like WM8741 or AK4396 that support master clocks up to 36Mhz (so 128fs is required)? This would support 176.4kHz and 192kHz sampling frequencies for those chips.

//Group0:Si570 frequency and *Fs combination for very low mclk range
{F112896, 256*FS}, //2 44.1 KHz
{F122880, 256*FS}, //3 48 KHz
{F225792, 256*FS}, //4 88.2 KHz
{F245760, 256*FS}, //5 96 KHz
{F225792, 128*FS}, //6 176.4KHz <---
{F245760, 128*FS}, //7 192 KHz <---
{F903168, 256*FS}, //8 352.8KHz
{F983040, 256*FS} //9 384 KHz

There is no LED for 128fs (I would have no problem with that) but it is probably too late to ask before GBIV. If it is so then I could get one double clock board for experiments with older chips.

Thank you.
That´s what i have in mind with my TDA1541A NOS, if i would use the Dual Clock with two Crystek CCHD-957 (22.5792 MHz/24.5760MHz) XO´s.

Is that possible with the Dual Clock?

44.1 kHz - 512*fs --> 22.5792 MHz
48.0 kHz - 512*fs --> 24.5760 MHz
88.2 kHz - 256*fs --> 22.5792 MHz
96.0 kHz - 256*fs --> 24.5760 MHz
176.4 kHz - 128*fs --> 22.5792 MHz
192.0 kHz - 128*fs --> 24.5760 MHz

Cheers,
Oliver
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Old 24th January 2013, 10:20 AM   #2234
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Thx Hochopeper. My intention was going for sync but if I2C is not available then obviously no cheap easy way to get it. I'm not sure if async would work with non ESS ICs.
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Old 24th January 2013, 10:21 AM   #2235
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Hi Oliver,

That is the functionality of the default jumper setting for the DualXO board. The generic clocks provided with the DualXO are exactly those frequencies. Refer to page 3 of Ian's DualXO manual.


Chris
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Old 24th January 2013, 10:29 AM   #2236
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Quote:
Originally Posted by hochopeper View Post
Hi Oliver,

That is the functionality of the default jumper setting for the DualXO board. The generic clocks provided with the DualXO are exactly those frequencies. Refer to page 3 of Ian's DualXO manual.


Chris
Thank´s Chris.
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Old 24th January 2013, 10:57 AM   #2237
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Originally Posted by iancanada View Post
Hi regal,
This I2S FIFO accepts true 16bit to 32bit I2S input range (actually sck input from 32fs to 64fs). Internally, the FIFO memory is true 32bit processing. Output sck is 64fs (I2S standard, same as most DIRs). No problem if you feed true 32bit I2S, bit perfect confirmed.
Have a nice weekend.
Ian
Quote:
Originally Posted by dvb-projekt View Post
That´s what i mean. The TDA1541A limit for BCK (SCK - FIFO out) is 6.4 MHz.

If FIFO´s SCK = 64*FS than we have:

44.1 KHz --> 2.8224 MHz
48 KHz --> 3.720 MHz
88.2 KHz --> 5.6448 MHz
96 KHz --> 6.144 MHz
176.4 KHz --> 11.2896 MHz
196 KHz --> 12.544 MHz

If this above is correct, i couldn´t use the 176.4 and 196 KHz sampling rates.
My last concern driving the NOS TDA1541A with 176.4 kHz and 192 kHz.

As the FIFO SCK output is 64fs and i think the SCK output of the Dual Clock is equal, correct?

If so i could cancel these two sampling frequencies, unless the SCK would be switched to 32fs.
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Old 24th January 2013, 05:46 PM   #2238
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Quote:
Originally Posted by dvb-projekt View Post
My last concern driving the NOS TDA1541A with 176.4 kHz and 192 kHz.

As the FIFO SCK output is 64fs and i think the SCK output of the Dual Clock is equal, correct?

If so i could cancel these two sampling frequencies, unless the SCK would be switched to 32fs.
When we talking about xFs, we mean the relationship between MCLK frequency and Fs .

TDA1547 is running at NOS mode do not need a MCLK, so xFs parameter is meaningless for TDA1541. Please just think about it .

Ian
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Last edited by iancanada; 24th January 2013 at 06:11 PM.
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Old 24th January 2013, 06:09 PM   #2239
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Quote:
Originally Posted by dvb-projekt View Post
My last concern driving the NOS TDA1541A with 176.4 kHz and 192 kHz.

As the FIFO SCK output is 64fs and i think the SCK output of the Dual Clock is equal, correct?

If so i could cancel these two sampling frequencies, unless the SCK would be switched to 32fs.
I guess you are concerned about true 16bit I2S (in which sck=32Fs) and 32bit I2S(sck=64Fs) issue.

I confirmed many times, TDA1541 accept 32bit I2S (with 16 bit data) without any problem, That's the native feature of Philips I2S protocol .

But if you are thinking it would be better feed TDA1541 with true 16bit I2S, that's fine. In this case, I would suggest you useing the I2S to PCM daugher board after clock board. The daughter board was specially designed for DACs running at NOS mode. It's not only capable for true 16bit output, but also can stop clock after loading data in order to minimizethe noise floor.

But unfortunately it's still not available for GB so far.

Ian
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Old 24th January 2013, 11:42 PM   #2240
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Default Si570 Clock Board -Native support DACs in dual mono

Si570 clock board was designed be capable to support DACs in dual mono configuration natively.

It has two MCLK u.fl output sockets with drivers independent from each other. Each of the sockets was driven by a dedicated clock driver to ensure high quality low jitter MCLK signals being fed into both DAC blocks. Carefully designed PCB layout matches the impendence to 50ohm transmission lines which optimized to the good signal integrity (SI) driving u.fl coaxial cables.

Additional group of u.fl socket footprints of I2S output signals for the second mono block were placed at back side the PCB. Each I2S output signal has its own source termination network to reduce both reflection and cross talking.

To run DAC in dual mono mode, I’m highly recommended using u.fl coaxial cables with same length to guarantee signals arrive at each block at same moment. Please keep in mind, every 1 inch 50ohm coaxial cable will cause roughly 120ps delay on signal!

That’s one of the black magic of a digital cable: vibration and jitter

Ian
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File Type: jpg Si570Dual_MCLK.JPG (381.5 KB, 299 views)
File Type: jpg Si570_DualI2Soutput.JPG (281.1 KB, 289 views)
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Last edited by iancanada; 24th January 2013 at 11:52 PM.
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