Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 220 - diyAudio
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Old 21st January 2013, 06:30 AM   #2191
qusp is offline qusp  Australia
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the idea is to have a an inverted phase MLCK (synchronous is from fifo) and also play with inverting (or not) the phase of the DPLL, which would naturally be synchronised/locked with the MCLK. 'locked' or not, it would still be in its default phase setting (upward/rising stroke) the idea is to see how beneficial it may be to switch that to the falling edge
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Old 21st January 2013, 06:49 AM   #2192
glt is offline glt  United States
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Quote:
Originally Posted by qusp View Post
the idea is to have a an inverted phase MLCK (synchronous is from fifo) and also play with inverting (or not) the phase of the DPLL, which would naturally be synchronised/locked with the MCLK. 'locked' or not, it would still be in its default phase setting (upward/rising stroke) the idea is to see how beneficial it may be to switch that to the falling edge
I know the intention of the experiment. What I don't know is how is "locking to rising or falling edge of the bitclock" (inverting or not inverting the phase of the DPLL) related to the master clock in synchronous mode
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Old 21st January 2013, 08:09 AM   #2193
qusp is offline qusp  Australia
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do you think the DPLL vanishes? still? the DPLL loop is still active, it just doesnt have a whole lot to do, it effectively does nothing, but it is not switched off.

there is no Sync mode, or Async mode on ESS, you can only present it with conditions that mean it acts synchronously

the point being, that perhaps one of them is cleaner.

Last edited by qusp; 21st January 2013 at 08:13 AM.
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Old 21st January 2013, 08:15 AM   #2194
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Hang on, now I'm confused, is the DPLL locking to mclk or bit clock?
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Old 21st January 2013, 08:52 AM   #2195
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Originally Posted by Popolvár View Post

How did you connect the EXA to the fifo? Did you use the isolator board to isolate clock & reclocker & dac grounds from the digital input ground? Does exaU2I have the impedance matching resistors on outputs?

The EXA board has optical isolation at output. As there is no onboard reclocking following the isolators, they are probably the main source of jitter. Yet, having tried most of the USB/I2S boards in manufacture, the EXA is to my ears head and shoulders above the rest. Entirely subjective opinion, of course.
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Old 21st January 2013, 08:55 AM   #2196
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analog_sa, it seems you are stuck in the 90's-00's when the recovered spdif clock actually meant something?
It was my omission not to notice the words "Ian's spdif" in the post i replied to. Sorry for all the confusion my post brought, i simply meant a generic spdif with a recovered clock.

Last edited by analog_sa; 21st January 2013 at 09:00 AM.
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Old 21st January 2013, 10:24 AM   #2197
qusp is offline qusp  Australia
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Originally Posted by hochopeper View Post
Hang on, now I'm confused, is the DPLL locking to mclk or bit clock?
as I understand it (which isnt very deeply I must admit), probably both, it will be resolving the difference/relationship between them, thus why it freewheels when they are in sync.
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Old 21st January 2013, 03:59 PM   #2198
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Originally Posted by qusp View Post
the idea is to have a an inverted phase MLCK (synchronous is from fifo) and also play with inverting (or not) the phase of the DPLL, which would naturally be synchronised/locked with the MCLK. 'locked' or not, it would still be in its default phase setting (upward/rising stroke) the idea is to see how beneficial it may be to switch that to the falling edge
As I understand, there is no any real PLL or VCO inside ESS DAC. My point might be wrong, but I think their DPLL concept is totally an ASRC algorithm, or could be looked upon as a kind of digital filter. At async mode, all data is calculated/estimated in 32bit resolution according to output of phase comparator. At sync mode (phase comparator output is 0), real data picked up from each Fs point and interpolating data placed in between to up-sample music into higher Fs. The accuracy determined by both DSP data length (32bit is highest so far) and the MCLK frequency. That why higher MCLK result in better SQ on ESS DAC.
Nobody knows the actual details except the designers. Besides, what we can do I think is just trust your ears to find out which way is better, MCLK inverting or normal, and software lock to raising or falling edge.

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Old 21st January 2013, 07:58 PM   #2199
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Hi Ian,

Makes a lot of sense.

I've observed the value of the 32-bit dpll in asynch mode and it varies quite a bit all the time. As one increases the bandwidth of the dpll, the variations get larger.

It may be obvious, but may I ask the question: in asynch mode with the inherent error from the DPLL value, is higher mclk frequency necessarily more accurate? or there is a sweet spot at certain frequency?
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Old 21st January 2013, 11:33 PM   #2200
Bunpei is offline Bunpei  Japan
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Originally Posted by iancanada View Post
As I understand, there is no any real PLL or VCO inside ESS DAC. My point might be wrong, but I think their DPLL concept is totally an ASRC algorithm, or could be looked upon as a kind of digital filter. At async mode, all data is calculated/estimated in 32bit resolution according to output of phase comparator.
I have the similar speculations.

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Originally Posted by glt View Post
I've observed the value of the 32-bit dpll in asynch mode and it varies quite a bit all the time. As one increases the bandwidth of the dpll, the variations get larger.

It may be obvious, but may I ask the question: in asynch mode with the inherent error from the DPLL value, is higher mclk frequency necessarily more accurate? or there is a sweet spot at certain frequency?
There might be three aspects.

The MCLK frequencies of 512 x, 1024 x, 2048 x fs or near to these are apparently sweet spots as they create almost the same situations as a synchronous MCLK does.

The DPLL value register holds a count value of BCLK in 32 bit unsigned integer of which full scale, 2^32-1, matches to MCLK counts. The higher MCLK frequency is, the smaller the count value becomes. Therefore, a higher MCLK frequency should allow a lower DPLL bandwidth for the same fs.

ES9018 assumes the time interval given by MCLK is absolutely correct and constant. However, an actual clock has a certain fluctuation. The relative stability between BCLK and MCLK is important. The MCLK source of higher frequency tends to have the larger phase noise. There might be an optimum points.

Last edited by Bunpei; 21st January 2013 at 11:46 PM.
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