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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
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Old 21st January 2013, 01:20 AM   #2181
hochopeper is offline hochopeper  Australia
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Hi Ian,

I was just reading the ES9012 datasheet and found a paragraph on page 12 that might be interesting to you there is a paragraph titled: DPLL Frequency Phase Flip. Register 17 can be used to set the DPLL to lock to rising or falling edge of the clock.

In your experiments with Si570 inverted mclk have you been able to adjust that DAC Register also?


Cheers,
Chris
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Old 21st January 2013, 01:28 AM   #2182
iancanada is offline iancanada  Canada
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Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter
Quote:
Originally Posted by hochopeper View Post
Hi Ian,

I was just reading the ES9012 datasheet and found a paragraph on page 12 that might be interesting to you there is a paragraph titled: DPLL Frequency Phase Flip. Register 17 can be used to set the DPLL to lock to rising or falling edge of the clock.

In your experiments with Si570 inverted mclk have you been able to adjust that DAC Register also?


Cheers,
Chris
Can you send me the pdf ? FIFO does not change the ESS register. If your have external control, you can give a try by software. I'm interested in your result.

Regards,

Iian
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Old 21st January 2013, 01:32 AM   #2183
hochopeper is offline hochopeper  Australia
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A few logistical challenges there ... first is that I don't have a 9012 DAC yet nor do I have an Si570 yet either

I was doing research for a remote control I am starting to build for Acko's DACs at the moment and stumbled across that in the datasheet.

Cheers,
Chris
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Old 21st January 2013, 04:01 AM   #2184
qusp is offline qusp  Australia
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yes i've played with that, however i'm unsure as to my conclusion... dont know how to put into words
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Old 21st January 2013, 04:17 AM   #2185
glt is offline glt  United States
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The register setting is in the data sheet. I've also implemented DPLL phase inversion in my code, but I can't tell the difference (with my ears)
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Old 21st January 2013, 04:23 AM   #2186
hochopeper is offline hochopeper  Australia
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Flipping that around without changing the clock I wouldn't have expected night and day changes. The point I was making is that with inverted mclk from Si570 I think you might want the DPLL synching to the falling edge and for 'normal' mclk then rising edge would make sense.


See the scope shots of Ian's in Post #1606


Regardless I think we're getting to the thin end of the list of improvements perhaps already so all of the night and day changes are probably way back in the past.

Cheers,
Chris
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Old 21st January 2013, 04:25 AM   #2187
qusp is offline qusp  Australia
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yeah thats what he said, ie where he got the info from; as did I but if there is a difference I find it hard to elucidate. it was far from a controlled test though, just changing the register while audio was playing.

'the wire' plus JH13 in ears is a pretty good lens to pick changes. it did appear to change the sound slightly, but yes perhaps its best saved for si570 experiments

I did also flip the phase on titan

Last edited by qusp; 21st January 2013 at 04:27 AM.
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Old 21st January 2013, 04:57 AM   #2188
glt is offline glt  United States
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Quote:
Originally Posted by hochopeper View Post
Flipping that around without changing the clock I wouldn't have expected night and day changes. The point I was making is that with inverted mclk from Si570 I think you might want the DPLL synching to the falling edge and for 'normal' mclk then rising edge would make sense.


See the scope shots of Ian's in Post #1606


Regardless I think we're getting to the thin end of the list of improvements perhaps already so all of the night and day changes are probably way back in the past.

Cheers,
Chris
Asynch or synch?
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Old 21st January 2013, 04:58 AM   #2189
qusp is offline qusp  Australia
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sync, the idea is to play with the phase relationship between a synchronous inverted MCK input and an inverted/non-inverted phase DPLL

how could it be async? it wouldnt have an mck to input if it was async
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Old 21st January 2013, 05:19 AM   #2190
glt is offline glt  United States
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sync, the idea is to play with the phase relationship between a synchronous inverted MCK input and an inverted/non-inverted phase DPLL

how could it be async? it wouldnt have an mck to input if it was async
I don't know the relationship between all the clocks. DPLL locks to bitclock in asynch. In synch, it is always "locked" to the bitclock
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