Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

[TNT]

Originally Posted by analog_sa

Did i in any way suggest otherwise?

OK, You ment that it can support higher samplings rates?

/

[Popolvár]

Originally Posted by analog_sa

Of course the EXA is a much higher quality source than any recovered from spdif signal has any hope to be.

Do you have more info for this claim?

How did you connect the EXA to the fifo? Did you use the isolator board to isolate clock & reclocker & dac grounds from the digital input ground? Does exaU2I have the impedance matching resistors on outputs?

Why I am asking - I have looked at the output terminal of the exaU2I (on their web) and well, how to say it, this is probably good enough for connecting a relay but not a high frequency digital signal. So it is hard to say what is the digital signal quality that is passed to your dac.

I would not like to start a flame war but I think that it would be fair to Ian's work to use the same professional and detailed approach as he is using, when posting judgements.

[qusp]

analog_sa, it seems you are stuck in the 90's-00's when the recovered spdif clock actually meant something? the recovered spdif clock is not used with fifo, it is discarded altogether, not reclocked. so your statement doesnt make a great deal of sense and as shown, it was the spdif input reclocked, with the generic clock, to have less than 5ps.

your subjective opinion is just that, a subjective opinion; which you are welcome to, but making statements like the above based on it.... sorry but it holds no water whatsoever

Originally Posted by popolvar

Do you have more info for this claim?

of course not

[qusp]

DP

[qusp]

Originally Posted by sp502

I am curious to know why you and others are referring to the 2.5ns jitter of the XMOS chip (could be any other chip as well) as a "problem".
Do you believe that the proper and/or unique point for perfect timing accuracy should be at the chip that "translates" USB data to I2S signals?
Why to try to be perfect in timings close to the source? Should we go back to the synchronous USB transports as well?
If you use a very simple I2S re-clocking circuit, similar to the ones found here, don't you get excellent results?
(Of course there are some limits of the amount of jitter that can be compensated, but I believe 2.5ns is orders of magnitude lower).

I think that many times there are exaggerated comments about the performance of some components without the proper justification.
Many functions may be performed in various points of a telecommunication chain/system (and audio reproduction may be considered as one).
Fortunately the contemporary digital systems provide excellent mechanisms that assist the design of a system that has not to be perfectly synchronous from the one end to the other.

Ian's design proves that there are ways to connect two different clock domains and get perfect results, with the only constraint of the buffer size.
But if you use the same clock for both the USB to I2S conversion system and the DAC, one very simple re-clocking system is enough (no buffer is needed).
The DAC will get all the bits jitter-free and you can have the clock(s) and re-clocking mechanisms really close to the DAC where is more important.

"Problems" like this should be the boost for better circuit designs that may not be simpler, but may provide better results than the "simplistic" ones.

it is an issue when its being used directly, as with some designs, particularly when it is being used directly with BCK as the only clock...

also just because its horrible jitter can be fixed, as it can here with fifo, doesnt cure it of its sins. not all designs have a proper reclocking stage, some use separate MCK and the rest of the lines directly from xmos. in any measure 2.5nS is HUGE 100-1000x higher than any of the devices that were claimed as horrible digititus inducing audio nightmares. some of those same people have been using the 2.5nS output without reclocking and claiming how 'liquid' and 'organic' sounding it is....

proper reclocking is not included in its reference design is it?

[qusp]

Originally Posted by Adrculda

Yes I agree, but a lot better to hear the noise in the higher audio band where its will be more pronounced. I would rather have it where its nearly inaudible rather than in the 8K - 20K range....

umm, no youve got it backwards, the higher speed xo fs noise is LESS audible than the lower. you dont here the noise, you hear its effect in the time domain. so actually 50-200Hz is the most sensitive region, because it is in this area that dacs, the clock and other parts of the circuit have their lowest PSRR

[bigpandahk]

Originally Posted by iancanada

How about coaxial source?

Ian

both the opt and coaxial have the same problem, lock LED "on" without sound from BIII. The FIFO "empty" On. I have used other DAC to confirm the opt source has music.

[sp502]

Originally Posted by qusp

it is an issue when its being used directly, as with some designs, particularly when it is being used directly with BCK as the only clock...

also just because its horrible jitter can be fixed, as it can here with fifo, doesnt cure it of its sins. not all designs have a proper reclocking stage, some use separate MCK and the rest of the lines directly from xmos. in any measure 2.5nS is HUGE 100-1000x higher than any of the devices that were claimed as horrible digititus inducing audio nightmares. some of those same people have been using the 2.5nS output without reclocking and claiming how 'liquid' and 'organic' sounding it is....

proper reclocking is not included in its reference design is it?

XMOS reference design reclocks only the SPDIF signal, not the I2S.
But my question remains, do you believe that the proper and/or unique point for perfect timing accuracy should be at the chip that "translates" USB data to I2S signals?
Have you measurements of other similar USB to I2S solutions?
The existence of non-optimum implementations is the whatever chip to blame or the designer of the implementation?
[Another issue is how much the jitter in I2S signal affects the performance of various DACs, are all affected the same way and in the same magnitude?]

My point is to concentrate on the complete design of a system and not on the individual components.
There are devices, out there and in this forum, that prove that good designs do give excellent results even with "problematic" components.

[qusp]

oh I agree on the whole system approach, but the fact the reference design does not call for it and thus has 2.5ns jitter on its output is quite atrocious. they do not make it clear that you should expect this much jitter and take precautions, so there will be MANY xmos based designs that simply reclock MCLK and leave the other chaos intact. 2.5ns is massive, it never would have been accepted even on a recovered spdif clock.

the reference design has an MCLK, so it is not unreasonable to expect the MCLK and i2s to be worth using... hell from my brief glance at the materials they use it directly on their ref designs that have multichannel dac output....

there is nothing saying, btw the i2s has 2.5ns jitter, best you finish the job for us...

[iancanada]

Originally Posted by bigpandahk

both the opt and coaxial have the same problem, lock LED "on" without sound from BIII. The FIFO "empty" On. I have used other DAC to confirm the opt source has music.

If "EMPTY LED" is on that means the I2S signal is wrong. Did it work before? Please see the signals by a scope to find out what's wrong with the I2S.

Ian