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Old 17th January 2013, 10:01 PM   #2141
Telstar is offline Telstar  Italy
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1) true.
2) i dont understand your explanation very well.
I think to get that it would be better for noise due to smaller current draw?

I2s isolation has one issue: added jitter. Does your FIFO board prevents this?
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Old 17th January 2013, 10:06 PM   #2142
TNT is offline TNT  Sweden
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Feels like confusion between isolation as in fifo/regeneration vs. isolation as in galvanic - no?
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Old 17th January 2013, 10:32 PM   #2143
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by iancanada View Post
I have a WaveIO USB. But Iím not happy with the 2.5ns jitter problem on I2S output caused by XMOS, though itís no longer an issue working with my FIFO.
Have you measured the "2.5ns jitter" by yourself? Have your FIFO completely eliminated the sound degradation caused by the jitter?

I think the 2.5ns is four times better than the minimum time tick that ES9018 has with 100MHz asynchronous MCLK.
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Old 17th January 2013, 10:46 PM   #2144
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Quote:
Originally Posted by Bunpei View Post
Have you measured the "2.5ns jitter" by yourself?
YES

Quote:
Originally Posted by Bunpei View Post
Have your FIFO completely eliminated the sound degradation caused by the jitter?
For the jitter caused by XMOS, I think so, but try it by yourself if it is possible

Quote:
Originally Posted by Bunpei View Post
I think the 2.5ns is four times better than the minimum time tick that ES9018 has with 100MHz asynchronous MCLK.
Do you mean ESS9018 does not care about the 2500ps jitter from the SCK/BCK, WS/LRCK?

Regards,

Ian
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Old 18th January 2013, 11:15 AM   #2145
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by iancanada View Post
YES
It's amazing! You must be the only person who measured actual and accurate jitters in this community. How respectful!

By the way, what RMS value did you obtain in which frequency range? I think 2.5ns is the maximum value and the density distribution between zero and 2.5ns would be uniform. The RMS value is supposed to be get small.

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Originally Posted by iancanada View Post
For the jitter caused by XMOS, I think so, but try it by yourself if it is possible
Sorry. My current interest is only on plays of DSD256/512 sources.

Quote:
Originally Posted by iancanada View Post
Do you mean ESS9018 does not care about the 2500ps jitter from the SCK/BCK, WS/LRCK?
My speculation is like this;
ES9018 architecture can not generate any shorter timing event than MCLK interval. Their "jitter reduction" functionality is not a fine adjustment along time axis but an interpolation of sound intensity values.

I only apply a synchronous master clocking scheme to the DAC chip. In this case, we can make the timing gap to zero.

By the way, are you engaged in development of FDA regulated medical devices?
I am working with a regulatory agency in Japan. I respect your design style very much.
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Old 18th January 2013, 11:42 AM   #2146
regal is offline regal  United States
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Originally Posted by iancanada View Post
I can see there are two reasons:

1, Most of the USB isolators we can touch currently are for USB2.0 full speed 12MHz, not for high speed which is 480MHz. In this case, it will degrade the performance of many good USB audio interfaces which were designed optimizing for 480Mhz high speed, especially for higher Fs application as 192KHz and 384Khz.

2, Even when high speed USB isolator becomes popular down the road, I2S/DSD will still be the better solution than the USB isolator. The reason is very clear. Since we have to power the isolated section from DAC side, powering half I2S/DSD isolator comes with much less noise than powering a whole USB interface. The USB interface usually needs a couple of clocks with different frequency running at same time, not only drawing more current, but also introducing much more EMI noise from power supply and ground.

Ian

The other advatage I see most is we are isolating the Fifo's 600MHZ "computer" by this method. If we were to isolate at the USB side little would be gained.


On another subject that I've been running into, would there be any possibilty to offer that HDMI LVDS I2S output. I know its not technically the best but it just seems to be something worth offering, I know this has been discussed before and several arguments were made against it but is there any chance of revisting that discussion ? I do see an advantage in a balanced i2s as far as rfi and ground loops. What are the disadvantages?
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Old 18th January 2013, 12:15 PM   #2147
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The other advatage I see most is we are isolating the Fifo's 600MHZ "computer" by this method. If we were to isolate at the USB side little would be gained.
I agree that Ian's bi-directional FIFO isolator board is excellent. But I think you've missed the design they're talking about here as 'this method'. They are currently referring to Ian's new generic isolator for use between transport device and the FIFO input. Ian's design posted here - Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter It's been buried quickly in a couple of pages of posts so you probably missed it by not quite reading far enough back, easy to do in a fast moving thread!!

I have no opinion on HDMI LVDS I2S at this stage so I'm not ignoring your question, just don't know enough about it to give a meaningful/useful opinion.
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Old 18th January 2013, 03:51 PM   #2148
glt is offline glt  United States
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Originally Posted by Bunpei View Post
It's amazing! You must be the only person who measured actual and accurate jitters in this community. How respectful!

By the way, what RMS value did you obtain in which frequency range? I think 2.5ns is the maximum value and the density distribution between zero and 2.5ns would be uniform. The RMS value is supposed to be get small.

...
Hi Bunpei,

There were other measurements done by fetaudio.com a while back. (not to take any credit away from Ian -who in addition has made the only measurement I know of the 8805 aside from the manufacturer)
Seemed on the high side at the time, since one can expect "hundreds of psec" p-p, but the Xmos device has been well received by the audio community so didn't think too much about it.

This 2.5 nsec RMS comes as a surprise.
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Old 18th January 2013, 09:59 PM   #2149
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Originally Posted by glt View Post
Hi Bunpei,

There were other measurements done by fetaudio.com a while back. (not to take any credit away from Ian -who in addition has made the only measurement I know of the 8805 aside from the manufacturer)
Seemed on the high side at the time, since one can expect "hundreds of psec" p-p, but the Xmos device has been well received by the audio community so didn't think too much about it.

This 2.5 nsec RMS comes as a surprise.
Quote:
Originally Posted by Bunpei View Post
It's amazing! You must be the only person who measured actual and accurate jitters in this community. How respectful!

By the way, what RMS value did you obtain in which frequency range? I think 2.5ns is the maximum value and the density distribution between zero and 2.5ns would be uniform. The RMS value is supposed to be get small.
Yes, I'm not the fist one found this problem. Actually I didn't notice it at beginning because I use it as fifo input and the 2.5ns jitter was just within sweet range, I didn't feel anything wrong. After I post the pictures of WaveIO and FIFO, a guy asked me if I noticed the jitter issue, he did some test on his scope but he was not quite sure. I didn't believe that until I google "XMOS 2.5ns jitter problem". I was quite surprised. So, I did some measurement, unfortunately it was approved true. Actually the jitter histogram has two peak with 2.5ns time interval in between. Not the normal concept Gaussian jitter which is caused by the quality of XO. Obviously it's kind of determined system jitter caused by the processor. But I wouldn't post result of the screen shot, it's not fair. WaveIO is a very good design with nice layout and has nothing to do with this problem. It's totally the XMOS problem.


Quote:
Originally Posted by Bunpei View Post
Sorry. My current interest is only on plays of DSD256/512 sources.



My speculation is like this;
ES9018 architecture can not generate any shorter timing event than MCLK interval. Their "jitter reduction" functionality is not a fine adjustment along time axis but an interpolation of sound intensity values.

I only apply a synchronous master clocking scheme to the DAC chip. In this case, we can make the timing gap to zero.

By the way, are you engaged in development of FDA regulated medical devices?
I am working with a regulatory agency in Japan. I respect your design style very much.
Glad you like my design. They are medical grade .

Good to know you work for FDA agency. Yes, we are involved in FDA registration each time when we release a new product. As well as CE. From next week, I'll work for two weeks with a local testing labs for the EMI,EMC and safety test on another new release. Just cross your fingers

Have a nice weekend.

Ian
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Last edited by iancanada; 18th January 2013 at 10:22 PM.
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Old 18th January 2013, 11:11 PM   #2150
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Ian, thanks for taking the time to look into it.
Did you get a chance to measure the Amanero unit as well?

Fingers crossed for your tests. Good results will probably bring us closer to GB4 which can only be a good thing!
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