Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

[...]With 4 trailing clocks only PCM1702 would benefit of the stopped mode operation while for PCM1704 would be similar to continuous clock mode.
As PCM1704 is the newer and seems to be used by more diyers I would better support this - so to have 2 trailing clocks. But it's all one for me.
[...]
Fully agree, PCM1702 users could use the continuous clock operation.
Sometimes, compromises must be made, and this one is a small compromise, as LE and DATA are quiet anyway during conversion also with continuous clock.
 
Master clock

Ian, friends,

a few years ago I bought an XO3 from Guido Tent, to use it to reclock CD PRO SPDIF, but if I'll feed directly FIFO buffer from CD PRO I2S data it become available for other applications.
Do you think that I can use XO3 as master clock in FIFO buffer?

Anyone has thought to use a PLL?

Andrea
 
Has the XO3 a VCXO / PLL? In that case, don't use it. The FIFO will be there to correct small frequency deviations.

PLL, being software or hardware, will have to lock on the incoming stream. So it will need either a VCXO (which has worse phase noise performance than a comparable XO) or a software solution with clock dividers and who knows what.

It's no way better than a FIFO with independent clocks (but they of course must be close enough in frequency not to overfill or empty the FIFO buffer).
 
Has the XO3 a VCXO / PLL? In that case, don't use it. The FIFO will be there to correct small frequency deviations.

PLL, being software or hardware, will have to lock on the incoming stream. So it will need either a VCXO (which has worse phase noise performance than a comparable XO) or a software solution with clock dividers and who knows what.

It's no way better than a FIFO with independent clocks (but they of course must be close enough in frequency not to overfill or empty the FIFO buffer).

Low jitter clocks

It has not PLL, it's based on Tentlabs XO module (I believe).

I thought to use PLL to evenctually reclock I2S output.
 
I'm not sure how you arrive at the +6dB phase noise from the logic. I would like to know.

In the testing I have done recently I'm seeing more issues around deterministic noise that random phase noise. I would use reclocking D latches, possibly the Potato stuff and run them on an isolated supply. It only takes a little supply noise to modulate a clock in a gate, especially when we are looking at -120 to -150 dB.

Hi Demian, How are you doing?

The number came from a RF engineer who's job connected to oscillators design. He did measurement by those house price phase noise
analyzers. But he didn't mention the testing condition, as well as it's phase noise floor or close in phase noise.

Based on your measurement, how much additive jitter (converted to phase noise) will be introduced into a second generation clock by a
flip-flop ( take div by 2 for example)? and how about the different kind of flip-flops?

Did you mean a latch introduce less jitter than the flip-flop under the same condition?

Regards,
 
Ian, friends,

a few years ago I bought an XO3 from Guido Tent, to use it to reclock CD PRO SPDIF, but if I'll feed directly FIFO buffer from CD PRO I2S data it become available for other applications.
Do you think that I can use XO3 as master clock in FIFO buffer?

Anyone has thought to use a PLL?

Andrea

Hi Andrea,
I'll upgrade the FIFO KIT supporting the left justified format before the second run.
I'm not familiar with XO3. If it is a good clock, you may feed it into the clock board of the FIFO KIT. Any re-clock before FIFO is useless. Because clock was isolated.
 
Low jitter clocks

It has not PLL, it's based on Tentlabs XO module (I believe).

I thought to use PLL to evenctually reclock I2S output.
My 2 cents on this as me neither knows Tent products well:
if I understand the XO3 is basically a clock module with a canned clock + a low noise regulator + some kind of spdif reclocking circuit - that's it.

Is your XO clock square shaped? if so it's an XO not VCXO.
What is the frequency of your XO clock? 11.2896 MHz or other?
Do you use this XO3 module with your CD-Pro? If yes - can you use your CD-Pro without this XO3 module?
 
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My 2 cents on this as me neither knows Tent products well:
if I understand the XO3 is basically a clock module with a canned clock + a low noise regulator + some kind of spdif reclocking circuit - that's it.

Is your XO clock square shaped? if so it's an XO not VCXO.
What is the frequency of your XO clock? 11.2896 MHz or other?
Do you use this XO3 module with your CD-Pro? If yes - can you use your CD-Pro without this XO3 module?

XO3 module replace CD PRO crystal oscillator and reclock spdif: to implement this module in CD PRO I have to remove crystal and relative caps, then I can take reclocked spdif from it.
I realize that I cannot use my XO3, clock frequency is 8.4672 Mhz compliant with CD PRO crystal clock, while I need 11.2896 for FIFO.
I think I can use CD PRO without this module because, as Ian said in a previous post, I feed FIFO buffer directly from CD PRO I2S data, so it was redundant.
 
XO3 module replace CD PRO crystal oscillator and reclock spdif: to implement this module in CD PRO I have to remove crystal and relative caps, then I can take reclocked spdif from it.
I realize that I cannot use my XO3, clock frequency is 8.4672 Mhz compliant with CD PRO crystal clock, while I need 11.2896 for FIFO.
I think I can use CD PRO without this module because, as Ian said in a previous post, I feed FIFO buffer directly from CD PRO I2S data, so it was redundant.
If you did not removed the original crystal oscillator from your CD Pro this XO3 module is indeed useless.
I hoped you can use the XO clock from it, but not with this frequency.

I'm wondering what is the bit clock of the I2S at the CD PRO out :confused:
 
Hi Andrea,
I'll upgrade the FIFO KIT supporting the left justified format before the second run.
I'm not familiar with XO3. If it is a good clock, you may feed it into the clock board of the FIFO KIT. Any re-clock before FIFO is useless. Because clock was isolated.

Hi Ian,

thanks for upgrade. Do you implement this feature in a new bord?

About PLL reclocking I meant after FIFO, before DAC or DF.
 
Hi Ian,
Regarding Andrea's CDPro - FIFO issue: if I understand well CDPro uses SAA7372 or SAA7374, both output I2S in 48bit format not 64, thus the output SCK according to the manual is 2.1168MHz
Can the FIFO handle this? - if not he can still use the spdif output of CDPro with your spdif board then the FIFO but not direct I2S
Thanks,
Zsolt
 
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Hi, Ian

Your FIFO+reclocker combined with Sabre dac is really impressive, especially when synchronous mode between the dac and reclocker.

When I first fired up SDTrans384 - FIFO plus reclocker( U1 is replaced with NDK NZ2520SD ) - Buffalo2 setup, I immediately noticed this obviously outperforms SDTrans384 - Buffalo2 combo.
Side by side comparison was never needed.

Now I can hear more low-level informations more easily and feel as if near the everything some more precise - bass are better controlled, less harsh Hi, and so on.

Really good job indeed, and I'm glad to see you still seek more improvement and versatility...


Thanks!
 
Hi guys.

Interesting project.

Let me ask you a question.

Pretty much all computer audio interfaces suffer of noise, jitter, intermodulations, drifts, you name it, fed from the PC or transport via USB, SPDIF, you name it.

Slightest optimizations (HW/SW) on the transport side usually have an impact on the sound. (See my Touch Toolbox effects, audiophile SW player effects, .wav vs. .flac., asf. asf.

I'm not aware of any audiointerface which wouldn't respond to those upstream optimizations.

Now. If for example I'd connect a Wave-IO XMOS USB interface (you might have followed discussions over here at DIY-audio) and the reclocker,
do you guys think, the impact of the upstream mess would be gone -- as long words and bits are the same????

Thx for your feedback.

Cheers
 
Hi Ian,
Regarding Andrea's CDPro - FIFO issue: if I understand well CDPro uses SAA7372 or SAA7374, both output I2S in 48bit format not 64, thus the output SCK according to the manual is 2.1168MHz
Can the FIFO handle this? - if not he can still use the spdif output of CDPro with your spdif board then the FIFO but not direct I2S
Thanks,
Zsolt

Hi Vzs,

My FIFO is 100% compatible with I2S standard. So, it doesn't matter how many sck per word or sck frequency. Any word length between true 16bit to true 32bit is working. Thank you so much for noticing me about that.

For Andrea's project, if that XO3 is just for upgrading CDPro, then with the FIFO attached, I don't think he need it. He just need connect the I2S output directly from the CDPro into the FIFO.
 
Same as for the others - see page 18: for 1xfs the SCLK = 2.1168MHz or multiples of this so 48bit I2S frame.
Let's wait to see what Ian says about this. In worst case you use the spdif out of CDPro to spdif board of FIFO.

I've seen the datasheet, 2.1168 x n.
Spdif in not the best solution, I2S is definitely a cleaner solution, but if no other solution I'll use spdif.

Well, I'm waiting for Ian impression about this.
 
Hi Vzs,

My FIFO is 100% compatible with I2S standard. So, it doesn't matter how many sck per word or sck frequency. Any word length between true 16bit to true 32bit is working. Thank you so much for noticing me about that.

For Andrea's project, if that XO3 is just for upgrading CDPro, then with the FIFO attached, I don't think he need it. He just need connect the I2S output directly from the CDPro into the FIFO.

Ian

Good news for me!
at this point is missing only to feed directly NPC, so my project will be complete.

Thanks