This night I had a vision : did you checked the soldering at the bottom of the Pi /I2S adaptator and the 40 pins plug ? A cold joint ? (if the midle led on the FIFO doesn't lock green this is because it don't see the I2S signal or just a part of it !) : I had this problem with an uf-l wire but as you buzzed yours already it can be below the I2S adaptator when you soldered it on the black plug !
Dunno, Worth to buzz it as well !
Dunno, Worth to buzz it as well !
Worth checking that again 
I did already. But for now, im just checking my whole setup without the PI as output. The XO1 itself is not working properly yet. So going to dig into that first, and try building up the "ideal" situation step by step. Replacing the XOs with the Crystecs could solve the issue. As I know now, the FIFO board itself aint broken, it will be fun again debugging Cheers!
I did already. But for now, im just checking my whole setup without the PI as output. The XO1 itself is not working properly yet. So going to dig into that first, and try building up the "ideal" situation step by step. Replacing the XOs with the Crystecs could solve the issue. As I know now, the FIFO board itself aint broken, it will be fun again debugging Cheers!Dear experts,
Could someone please explain how FIFO works? If an input signal comes in on its clock and the same data comes out on a new low-jitter clock, then the frequencies of both clocks must match to avoid the buffer empty or full conditions. This is possible only in two cases. (1) The source is slaved by the reclocker and uses the reclocker's clock. For this to happen there should be a clock feed from the reclocker to the source, but I don't see it on Ian's diagram. Alternatively the source must accept control signals to stop and start transmitting based on the buffer level in the reclocker. I don't see such a control line either. (2) The reclocker is slaved by the source and adjusts its clock frequency to match the source clock. This would imply PLL or another mechanism of dynamically adjusting the frequency of the reclocker's clock. This would introduce larger jitter than single-digit picoseconds. Please clarify my confusion. I would appreciate it.
Alex
Could someone please explain how FIFO works? If an input signal comes in on its clock and the same data comes out on a new low-jitter clock, then the frequencies of both clocks must match to avoid the buffer empty or full conditions. This is possible only in two cases. (1) The source is slaved by the reclocker and uses the reclocker's clock. For this to happen there should be a clock feed from the reclocker to the source, but I don't see it on Ian's diagram. Alternatively the source must accept control signals to stop and start transmitting based on the buffer level in the reclocker. I don't see such a control line either. (2) The reclocker is slaved by the source and adjusts its clock frequency to match the source clock. This would imply PLL or another mechanism of dynamically adjusting the frequency of the reclocker's clock. This would introduce larger jitter than single-digit picoseconds. Please clarify my confusion. I would appreciate it.
Alex
Ian chose a large buffer for FIFO. The buffer/delay for 44.1K/16bit data stream is 0.74 sec! The two clock domains may not synchronize with each other, but the deviation is usually not over 500ppm (Red book spec?). So, a large buffer will do unless you are playing an extremely long music which may ran out of buffer in some cases. This is my understanding of Ian's work. Please correct me if I am wrong.
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Thank you for the explanation. Well... then, in the worst case of one clock +500ppm and the other -500ppm, at 192kbps the buffer would run from 50% to either zero or full every 100 seconds or every song. And then what happens when the buffer runs out? Does the reclocker pause for 0.37s to refill the buffer? Or skip 0.37s when the buffer is full? Otherwise there would be a constant noise at the output. It would be great if you or someone else could provide a bit more details on this synchronization.
How did you get the figure? If the two clock domains deviate with 1000ppm (worst case) in frequency, that's 1/1000 or 0.1% error. If the 50% fill factor is 0.74 sec, then we could probably get 0.74/0.001=740 secs before the buffer ran out or over-filled. That's more than 10 minutes. In reality, you won't see a clock with 500ppm accuracy. Regular XOs are rated <50ppm, and some are below 10ppm. Well, this is just my wild speculation.
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Since you said the buffer was 0.74, I assumed a 50% fill would be 0.37 at 44.1 or 4 times less at 192, say 0.1. The with 0.1% it gives 100 seconds or almost every minute. I agree with good clocks the number should be higher. However, the specs of some sources, like a PC, could be way off. In any case, if this is how FIFO works in concept, then I understand and appreciate the explanation. Thank you!
PS. So what happens exactly when the buffer hits 0% or 100%? I assume a pause or a skip to avoid a constant noise. Is this actually the case?
PS. So what happens exactly when the buffer hits 0% or 100%? I assume a pause or a skip to avoid a constant noise. Is this actually the case?
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I would have a similar question...is there any advise on how to integrate Hermes/Chronus with Ian's reclocker ? I love thecincept to get usb-chips out of the way by bbb/hermes/chronus, and have direct, high-quality i2s feeding ian' reclocker....
I would have thought the whole point of a reclocker is that it doesn't really matter what you feed it...
Smile....well...that is for sure not the case. I tried a lot of different sources and ended up with a alix1 and sotm usb card for the moment. a raspberry with volumio was really bad, a windows machine not nice either...it is like with cables....first you think it cant be, but than you see it makes a difference....in this case even more than cables.
Well, that is the plan...after reading some articles like this one
https://hifiduino.wordpress.com/2015/03/02/bbb-dac-developments/
I understood that the i2s signal quality can differ as well quiet a bit...in strength (low signal in raspberry) and clock quality/setup. That is why I would have assume that a bbbwith hermes and cronus would be the best source feeding into ian's reclocker as I am not sure if any other reclocking solution will match what I am used to....
https://hifiduino.wordpress.com/2015/03/02/bbb-dac-developments/
I understood that the i2s signal quality can differ as well quiet a bit...in strength (low signal in raspberry) and clock quality/setup. That is why I would have assume that a bbbwith hermes and cronus would be the best source feeding into ian's reclocker as I am not sure if any other reclocking solution will match what I am used to....
+1 for no usb
I went with BBB - acko isolator reclocker - Ian I2S to PCM. No doubt FIFO must be great.
After constantly tweaking PC source/usb cables/ you name it, i don't even think about the PC parameters now. I tried CICS/CMP, Alix, UBUNTU, then BBB with Volumio/Rune etc. SQ all was highly depended on an elusive combination of parameters. The elimination of usb plus the isolator reclocker finally took the source out of the equation.
I went with BBB - acko isolator reclocker - Ian I2S to PCM. No doubt FIFO must be great.
After constantly tweaking PC source/usb cables/ you name it, i don't even think about the PC parameters now. I tried CICS/CMP, Alix, UBUNTU, then BBB with Volumio/Rune etc. SQ all was highly depended on an elusive combination of parameters. The elimination of usb plus the isolator reclocker finally took the source out of the equation.
Supra,
Did you hear a significant difference when feeding your Pi with an external cell for IPhone VS a reg à la TS7A for instance ? (will all the chain : fifo-idolator-clock+pcm). Do you feed both clock & pcm boards with the same A123 cell ?
@ EVeryone
Does the FIFO supress the diference between a Windows or a Linux distro when USB source is still in use ?
Thanks,
regards,
Eldam
Did you hear a significant difference when feeding your Pi with an external cell for IPhone VS a reg à la TS7A for instance ? (will all the chain : fifo-idolator-clock+pcm). Do you feed both clock & pcm boards with the same A123 cell ?
@ EVeryone
Does the FIFO supress the diference between a Windows or a Linux distro when USB source is still in use ?
Thanks,
regards,
Eldam
I'm currently building a stupidly excessive over the top power supply to replace Raspberry's battery, i'll let you know how it goes, but I dont really expect any improvement, just want to prove it to myself.
Second question- NO. USB ****s everything up.
Haha, nice Supra,.. hope it actually makes a difference. For me, using a lineair does. Since I'm also feeding the S/PDIF board from it. The biggest improvement for me was using the clock board with a battery and isolator. Not the difference from standard clock to a crystek chd-957 2X Mhz. I think I'm going to hack the Schiit Gungnir to allow i2s inputs (can probably insert it where the USB board is. CMedia 6631A board is not the best anyways). Then perhaps I can have bigger differences.
Personally, i think it was really worth spending the money on it. Such a really big difference.
Personally, i think it was really worth spending the money on it. Such a really big difference.