Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 204 - diyAudio
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Old 11th January 2013, 05:27 AM   #2031
qusp is offline qusp  Australia
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hmm, I actually dont like the sound of this, interfering with the way the fifo main board chats with the DIX SPI doesnt seem wise to me, or is it just poling it for info? plus it would seem to be relying on having low level access to the fifo software?

I fear we are heading towards another impasse, where we are reminded that its a proprietary system that was developed here with us looking on lazily as designs magically appeared, not a project that was developed here in diyland.

so flexibility may mean the ultimate flexibility, if you catch my drift...

Adrculda: just for your info, Chris and I are loosely involved in an ongoing master control Micro for a multichannel dac/amp system, as we have many of the same boards, many of the same goals and live just up the road from each other

so i'm not just poking my head in with disapproving glances =)

Last edited by qusp; 11th January 2013 at 05:30 AM.
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Old 11th January 2013, 05:27 AM   #2032
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Originally Posted by Adrculda View Post
No misunderstanding here...
With the hifiduino in line with the right code of course, you can use it as a tool to see realtime whats going on... clock, fs, stream info and so on.

I understand this is Ians project, but some of us want a little bit more flexibility.
Actually now I think on it all of those things are available on LEDs now but not programatically via i2c/spi/etc. Also note that earlier in the development Ian has said that the control lines he uses now are shut to low power state during normal operation so I really think the FIFO stays as the master in all of this and anything else is a passive display device, not the active controller. Ian's already configured the ultimate, the flexibility of an extra controller comes at a sacrifice of tight integration and optimal implementation.

Is there really any functional flexibility missing here though? Other than cycling through inputs on the spdif board rather than selecting one directly? Because really, that is splitting hairs. Info not being available on a data bus isn't flexibility its just info display and really the least important part from my perspective. (other than my already stated desire to know the FIFO delay in near realtime so that it could be used to actively set the video sync)

Last edited by hochopeper; 11th January 2013 at 05:35 AM.
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Old 11th January 2013, 09:12 AM   #2033
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Hi Ian, as i understand from you histograms screenshots you are using LC584 right?
Quote:
I think you mean rise time of a scope is more important than the bandwidth on jitter measurement. But usually those two numbers are linked. Have you ever try the result reducing the bandwidth from 1GHz to 200MHz for a same jitter measurment?
no, youdont understand me. Jitter is interesting in band 10Hz to 10...100kHz, but HF spurs can in some DS dacs indirectly effect performanse, thats why interesting bandwith of our measurements can be up to 10Mhz.
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Do your mean the MCLK driver of the WM8805 is not good enough? What is the most optimized output impedance it was designed to drive into? I have a 1.8pf active probe, I can measure the 8805 output without load.
most real world devices not designet to work on 50ohm load, and for jitter measurement you dont need a 50ohm input. Use 1-10 400-500Mhz passive probe (active probe probably can add its own jitter, a have no such probes thats why i cant verify this)
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1. Apply ERES (3bit) function -- could you give a bit more details?
ERES or Enhanced Resolution is included in WP01 package (have you WP01 installed?), it is FIR low pass filter that filter and add more amplitude resolution (up to 11bits).
With this function you destoy several problems:
- amplitude-time distortion conversion
- not ideal timing for interliving ADC (in you scope you have (for 8Gs mode) 16 500Ms Philips ADCs working in time interliving mode, not perfect timing for each of it and you have frequency components 0.5, 1, 1.5....4Ghz modulated by our signal, you need to filter out this components for more correct jitter measurements)
- noise from FM radio, TV etc
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3. You signal must have maximim amplitude, just before clipping of ADC, use variable attenuator of you scope to maximize signal level. --- Yes it is, you are right. Did this way
this is needed to minimize amplitude-time distortion conversion, you can do a experiment to understand that it is a big problem, measure jitter signal with amplitude nead full scale and with amplitude 4times lower, compare results.
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4. Rise time of you signal should be 3-4ns for lowest osc jitter -- Now is around 0.9ns, too small?
Yes, use 200Mhz BW limiter in you scope.

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Old 11th January 2013, 11:22 AM   #2034
RollE2k is offline RollE2k  Sweden
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I have not read through the whole thread, but if i'm about to buy a buffalo dac, and want to use this FIFO board (and possibly XO), have i understand right that the FIFO board does not work with sample rates above 32/192KHz?
Also, if i want to take the easy way, i could just connect buffalo's clock to the FIFO board, and it would work? The XO-board would just make it take both the 44.1/48-multiple without resampling, if already have a good clock on the buffalo?

I'm quite new to dac-parts which is why i ask :-)
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Old 11th January 2013, 11:26 AM   #2035
qusp is offline qusp  Australia
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no, no , no
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Old 11th January 2013, 11:36 AM   #2036
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Originally Posted by RollE2k View Post
I have not read through the whole thread, but if i'm about to buy a buffalo dac, and want to use this FIFO board (and possibly XO), have i understand right that the FIFO board does not work with sample rates above 32/192KHz?
FIFO will do up to 352/384kHz sample rates with 32bit word length if I am correct (I'm not 100% certain on 24/32bit word lengths, pretty sure 32bit though).



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Originally Posted by RollE2k View Post
Also, if i want to take the easy way, i could just connect buffalo's clock to the FIFO board, and it would work? The XO-board would just make it take both the 44.1/48-multiple without resampling, if already have a good clock on the buffalo?

I'm quite new to dac-parts which is why i ask :-)

No. The FIFO will need a clock that is a direct multiple (256,512,1024) of the samplerate of the audio being played. You will need 2 clocks to cover 44.1 and 48 and their respective hi-res equivalents.

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I'm quite new to dac-parts which is why i ask :-)
We are all new at some point

The FIFO has a wiki now where I have tried to link to the respective manuals and different development projects that are underway by Ian, hopefully it will save you the hassle of reading the whole thread. I am hoping to spend some time adding more to the wiki this weekend.
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Old 11th January 2013, 11:47 AM   #2037
qusp is offline qusp  Australia
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yes its 32bit PCM but will accept 24bit and 16bit no problem.

whats wrong you dont like the minimalist new me Chris? you think it needed some fleshing out? too far?
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Old 11th January 2013, 11:49 AM   #2038
RollE2k is offline RollE2k  Sweden
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Thanks alot hochopeper, that was a really great answer, but the old 1.0 manual (the one on page 1) does say - 44.1 KHz, 48 KHz, 88.2 KHz, 96 KHz, 176.4 KHz, 192 KHz - 16bit, 24bit or 32bit, that is why i didn't think it could take 352/384kHz.

But still - would be possible to connect the FIFO directly to buffalo's clock, with the possiblity that maybe either 44.1 or 48kHz wouldn't work, since they are wrong multiple for the clock? Also what about DSD material, is that also supported?

Anyway, i'll try to check the wiki, and have a read there! Thanks again!
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Old 11th January 2013, 11:50 AM   #2039
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yes its 32bit PCM but will accept 24bit and 16bit no problem.
That's what I thought but hadn't read up enough on it because it doesn't effect my implementation of the FIFO.

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whats wrong you dont like the minimalist new me Chris? you think it needed some fleshing out? too far?
I am quite a fan of the zen-qusp! I just thought I'd try to save you writing it all out
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Old 11th January 2013, 11:54 AM   #2040
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Originally Posted by RollE2k View Post
Thanks alot hochopeper, that was a really great answer, but the old 1.0 manual (the one on page 1) does say - 44.1 KHz, 48 KHz, 88.2 KHz, 96 KHz, 176.4 KHz, 192 KHz - 16bit, 24bit or 32bit, that is why i didn't think it could take 352/384kHz.

But still - would be possible to connect the FIFO directly to buffalo's clock, with the possiblity that maybe either 44.1 or 48kHz wouldn't work, since they are wrong multiple for the clock? Also what about DSD material, is that also supported?

Anyway, i'll try to check the wiki, and have a read there! Thanks again!
Ahhhh I see that now, I think the manual to look at is the one for the DualXO board with double rate, that is where Ian describes the higher speed samplerate stuff.




Buff clock is 100MHz CCHD-950 right? Since it isn't a multiple of either then no, its not suitable. Also, the reclocking on Ian's XO boards is where the magic happens. so, yes, you do want the XO board! You will not achieve Ian's target performance without the reclocking stage integrated with the clocks the way he has designed it. They are really a package deal and unless you are just using one fs group (either multiples of 44.1 or multiples of 48) then you want the dualXO or Si570 clock boards, if you are just using one freq group then singleXO board may suit your needs.


DSD is not supported by current FIFO. Ian has said that current design cannot support DSD because the buffer memory size is too small DSD, will need larger FIFO buffer size and that DSD *might* be supported in the *possible* future multichannel FIFO design.

Last edited by hochopeper; 11th January 2013 at 11:57 AM.
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