Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 195 - diyAudio
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Old 5th January 2013, 12:55 PM   #1941
qusp is offline qusp  Australia
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yeah then the cap is not for the ADP151, but if you check the BOM (right next to the schematic), that position its also optionally a placement for TPS79333, for which pin 4 is the noise reduction/reference bypass pin. if you look at the schematic its also marked as NR, which gives us a clue.

I would have been very surprised if something like that got through Ians workflow, as annoying as that may be for us mere mortals haha

Last edited by qusp; 5th January 2013 at 12:59 PM.
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Old 5th January 2013, 02:00 PM   #1942
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some useful link:
Techniques for Measuring Phase Noise
Converts an oscillator phase noise curve to jitter information

For a 22.5792 CCHD-957 crystal oscillator from its phase noise showed in the datasheet, the calculated RMS phase jitter is around 0.3ps. Assuming the theorical -6dB for half the frequency we get around 0.15ps at 11.2896MHz.
From the HCD661 11.2896MHz OCXO specs the calculated RMS phase jitter is
around 0.03ps.
That's the reason to feed directly the DAC chip from the MCLK.
For those who have not yet understood, no difference if the DAC chip is fed from the source rather than the FIFO buffer, feeding the DAC BCK directly from MCLK you reach the best performance in jitter reduction.
This way can be implemented both if you run the DAC directly from the source either if you use an asynchronous re-clocking such as the FIFO buffer.

qusp,
you are right, I meant "Steinway", and I don't own this piano, I can't afford it
BTW, not very difficult to listen to a live performance in a theatre, at least in my land
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Old 5th January 2013, 02:03 PM   #1943
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Hi Ian

Are You planning to make 352.8Khz 384Khz version? Is this possible for that FIFO?

Stas

Last edited by StasioPe; 5th January 2013 at 02:21 PM.
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Old 5th January 2013, 02:47 PM   #1944
roender is offline roender  Romania
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Quote:
Originally Posted by qusp View Post
yeah then the cap is not for the ADP151, but if you check the BOM (right next to the schematic), that position its also optionally a placement for TPS79333, for which pin 4 is the noise reduction/reference bypass pin. if you look at the schematic its also marked as NR, which gives us a clue.

I would have been very surprised if something like that got through Ians workflow, as annoying as that may be for us mere mortals haha
Thank you

I presumed that unconnected pin4 conceal some undocumented noise reduction function and never presumed some mistake made by Ian
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Old 5th January 2013, 03:17 PM   #1945
qusp is offline qusp  Australia
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Quote:
Originally Posted by andrea_mori View Post
some useful link:
Techniques for Measuring Phase Noise
Converts an oscillator phase noise curve to jitter information

For a 22.5792 CCHD-957 crystal oscillator from its phase noise showed in the datasheet, the calculated RMS phase jitter is around 0.3ps. Assuming the theorical -6dB for half the frequency we get around 0.15ps at 11.2896MHz.
From the HCD661 11.2896MHz OCXO specs the calculated RMS phase jitter is
around 0.03ps.
That's the reason to feed directly the DAC chip from the MCLK.
For those who have not yet understood, no difference if the DAC chip is fed from the source rather than the FIFO buffer, feeding the DAC BCK directly from MCLK you reach the best performance in jitter reduction.
This way can be implemented both if you run the DAC directly from the source either if you use an asynchronous re-clocking such as the FIFO buffer.

qusp,
you are right, I meant "Steinway", and I don't own this piano, I can't afford it
BTW, not very difficult to listen to a live performance in a theatre, at least in my land
same here, we have classical music performances 'down under' as well.... but the suggestion that it has anything to do with our discussion of a home audio system is the confusing part, especially since its plain you have never played one, or even seen one close up, or you would know how it was spelled.

One does not come close to replacing the other, you are listening to one now? you can listen while reading, while eating, while talking with friends, while relaxing with your cat, or other feline type obsession? ;p it can spit out a righteous distorted bassline? my desires are sometimes, but definitely not always so civilised.

the rest, I really dont know what you are getting at, or what relevance it has to this thread. it really seems as if its you that is struggling to understand the subtleties of the post you objected to, what the strict definition of synchronised is, or what your 'solution' implies that is simply not very interesting to most of us. many who chose the fifo, did so in order to avoid the very topology you are describing. I want that performance level with ALL of my sources

As you admit, its the same, yet you are stuck with a single transport, playing CDs.... and CD's only. or you are suggesting some sort of slave clock MUX? No...

you can hear the difference between 0-0.5ps?, that would cause giggles from my direction. At this level, the differences are academic and we all (should) know it.

anyway look can we please stop this, I shouldnt have replied to you, i'm being civil (or as much as I can manage while you are having these somewhat condescending overtones in your posting) but its really off topic and nobody wants to read it and the 'tit for tat' aspect is apparently what I was warned for just before.... it can go on forever and we will never agree, so lets agree to disagree yes?

StasioPe: speeds up to 384kHz are already supported with the right dac/clocks

Last edited by qusp; 5th January 2013 at 03:37 PM.
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Old 5th January 2013, 05:06 PM   #1946
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Just a thought...
Was browsing through the Cirrus site when I tripped across Cobra Net!
Why not use cobra net to stream audio rather than USB ??

There's a 2ch, an 8ch and a 16ch version available!
And samples are available on request!
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Old 5th January 2013, 06:05 PM   #1947
percy is offline percy  United States
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Quote:
Originally Posted by iancanada View Post
Test1: WM8805 output MCLK jitter
....
Test2: MCLK jitter after FIFO
Hi Ian,
thanks for doing this, appreciate it. Got a question though -

Do you think doing the test on the bit or word clock would be more valuable than on the mclk ? Reason being mclk doesnt even pass through the fifo and fifo is like the "dut" of this test. Comapring the bit/word clock before and after would tell how much jitter it removed on those lines.
Right now its like comparing just the "good" clock (the actual clock) on the fifo board with the mclk coming out of wm8805.

Not that I am expecting any drastic difference in the result, but thinking maybe thats a more scientifically correct test ?
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Old 5th January 2013, 06:55 PM   #1948
qusp is offline qusp  Australia
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Quote:
Originally Posted by Adrculda View Post
Just a thought...
Was browsing through the Cirrus site when I tripped across Cobra Net!
Why not use cobra net to stream audio rather than USB ??

There's a 2ch, an 8ch and a 16ch version available!
And samples are available on request!
because USB, ethernet etc has more than enough bandwidth, I already do 8 channel hires async on USB. cobranet is not a standard of any kind as yet, we need another fractured 'standard' like we need cancer to become contagious.

cobranet has been mentioned a few times here already, cant remember the issues, but there were a few besides the proprietary nature. having only the ability to connect devices you built yourself would be a pita.

no thanks
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Old 6th January 2013, 03:42 AM   #1949
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Default S/PDIF receiver SCK jitter measurement report:WM8805 vs. FIFO

Test3: WM8805 output SCK jitter

Testing setup:

Jitter display: 50ps/DIV
see the first picture for details

Testing result:

Period jitter RMS:72.6ps
Period jitter peak-to-peak:+-250ps
Jitter distribution: Gaussian
frequency: 2.82232MHz

Please see the second screen shot picture for details

Test4: SCK jitter after FIFO

Testing setup:

Feeding WM8805 I2S output into FIFO, and then measure the output SCK of the asynchronized I2S stream.
Oscillators on the dual xo clock board: onboard generic 11.2896MHz XO
FIFO running at *256Fs
Jitter display: 10ps/DIV
Please see the third picture for details

Testing result:

Period jitter RMS:5.988 ps
Period jitter peak-to-peak:+-21ps
Jitter distribution: Gaussian
frequency: 2.82239MHz

Please see the fourth screen shot picture for details
Attached Images
File Type: png WM8805SCKJitterMeasureSetup.png (240.0 KB, 552 views)
File Type: png WM8805SCKjitter.png (32.0 KB, 472 views)
File Type: png FIFOSCKjitterMeasureSetup.png (249.2 KB, 468 views)
File Type: png FIFOSCKjitter.png (31.6 KB, 463 views)
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Old 6th January 2013, 11:53 AM   #1950
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Hi Ian,
great work!
Can you measure the jitter coming from the actual XO?
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