Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

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A

aive

Member
Joined 2013
Hey Ian, SUCCESS! All components up and running.

I've replaced the 45 Mhz supplied XO with Crystek 957 25 Mhz and it works well @ 44.1 Khz.

Question - Does the supplied 49 Mhz XO work? There is no audio when I playback at 192 Khz for example. I have ordered a 49 Mhz Crystek 957 and will replace when it arrives, but just checking to make sure.

What a long journey since putting my name down on GB, but well worth it :) Thanks Ian.
 
F

fordgtlover

Member
Joined 2007
Hi Ian

u.fl connectors on the WaveIO are the non-isolated. I recall that you said that we should use the isolated connection (pins). Did I misunderstand? Should I just use the non-isolated connection and not worry?

Cheers



iancanada said:
WaveIO already has output in u.fl sockets on it :)

I don't think you need a cap. It might be a new version?

Ian
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S

sidny

Member
Joined 2015
MeiT said:
hifirapsi SuperDAC


hifiraspi-10.jpg


hifiraspi-11.jpg
Click to expand...
Very nice system. Could you tell me more about the power supplies that you're using?
 
X

xaled

Member
Joined 2015
Thanks Ian.
Do you mean MCLK3 and MCLK2 On the dualXO II v7.5-A?
Do you have any specification on expected signal parameters?

Where can I find the latest documentation on the dual XO II board? The one on the GB first page is a bit outdated ;)

Is it possible to have I2S reclock output 1 to output only when reclocking from D3 or MCLK3 and I2S reclock output 2 to output only when reclocking from D4 or MCLK2?
The idea is to have two DACs connected to outputs 1 and 2. If incoming stream is x44.1 use dac one, if x48 use dac two.
 
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H

HpW

Member
Joined 2002
hpw-works.com
Reading July 2011:

1. The FIFO section
.Memory size: 4MB;
.FIFO half-full delay time: 0.743 seconds (for 44.1 KHz Fs);
.Half-full over flow time: 1486 seconds (at 44.1KHz input I2S stream with 500ppm frequency tolerance);
.Smart depth control strategy is integrated.
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Is there any detailed information available regarding the FIFO over/under run.
What will happen to the I2S if this happen?

Also, I would like to have on the front a LED flash/indication if this happens.

Any pointer would be useful regarding this over/under run.

Hp
 
iancanada

iancanada

Member
Joined 2009
twitter.com/iancanadaTT
Paid Member
HpW said:
Reading July 2011:



Is there any detailed information available regarding the FIFO over/under run.
What will happen to the I2S if this happen?

Also, I would like to have on the front a LED flash/indication if this happens.

Any pointer would be useful regarding this over/under run.

Hp
Click to expand...

Hi HP,

You can use FULL and EMPTY LED to indicate "over run" and "under run" . But normally it does't happen if FIFO has already locked to the input source.

Regards,
Ian
 
H

HpW

Member
Joined 2002
hpw-works.com
iancanada said:
You can use FULL and EMPTY LED to indicate "over run" and "under run" . But normally it does't happen if FIFO has already locked to the input source.
Click to expand...

Ian,

OK,

1. what happens to the output sample data if a "over run" and "under run" occurs. Are the previous sample data repeated or?

2. what is your "locked to the input source" condition, while you do not sync input & output sample rate (as I understand)

Hp
 
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