Get the shortest and thickest that you can. A few posts back someone got some 1.78mm from ebay and recommended them. I have bought these in the past:
sockets:
U.FL-R-SMT(01) - HRS (HIROSE) - RECEPTACLE, SMT, U.FL | Farnell UK
Cable assemblies:
U.FL-2LP-088K1T-A-(100) - HRS (HIROSE) - CABLE, PLUG/PLUG, 1.37MM, 100MM | Farnell UK
I've found mouser to be generally cheaper but they didn't have good u.fl cable selection when I looked.
Hi cls...
Can you post the item number that you bought as ebay links don't work from here and I can't find which ebay seller you used.
Cheers,
Crom
This seller makes custom cables.He said ''IPX(the same as U.F.L) cable assemblies can be cut to any length and attached to a variety of RF coaxial connectors''. SMA, 3G UMST EV-DO antenna items in connector store on eBay!,send them an email with the specifications of the cable and connector that you want,they will answer soon enough
Hi mcluxun,
The DC output from FIFO is filtered but registered. So, It should be close to the DC input. Please measure any of the decoupling caps, for example C2, C3 to see if there is 3.3V.
FIFO board has full set of protection circuits, it's not that easy to get damaged. I suggest you checking up all connections. But if you confirm it's really get damaged, you can sent it back to me to fix.
Good luck.
Ian
Thanks Ian.
I will play around a little more and see if I could get any further.
Is there any particular caps I should pay more attention to?
Thank you so much Demian for sharing those professional experience with us. It's very nice indeed!
I found jitter affects DS DAC and MultiBit DAC in different ways. DS DAC is more sensitive to the jitter on MCLK. Especially the 32bit ESS9018. Crystek CCHD-950 already has very good phase noise plot, but the audible difference is very obvious when I switch to OCXO which has even better phase noise performance. If there is limitation, it should be much higher.
Another thing is that, when we talking about the clock, for multi-bit or R-2R DAC, it's usually running at 1*Fs (or up to 8*Fs if there is oversampling filter in front), however, DS DAC, for example, ESS9018, MCLK runs at up to 1024*Fs or even 2048*Fs if f=90.xxx/98.xxx Mhz. So, if we are talking about jitter, they should be in totally different stories.
What's your point?
Thanks again,
Ian
Point 1 is that its more complex that it first appears. Making sure that what you are comparing is phase noise in the oscillator and not something else that is a side effect of the different oscillators would be the first step. Anything from a better buffer in the OXCO to noise radiated from the Crystec would need to be looked at. Is there a good (high isolation) buffer for the clock on the clock board? The ESS is a special case. They tell me that you can't really defeat the ASRC in it, it just works in different ways depending on the master clock. Mostly, it can better estimate the original sample rate with a higher internal clock. Its possible the math goes into overdrive when the clock to incoming signal ratios are very close multiples, the divisor will get really big. It would suggest that certain odd frequencies will work better than multiples of the incoming frequency (like the Benchmark example).
Multibit (ladder) dacs sync on the word clock edges so those must be really good. Delta Sigma DAC's run off the master clock but I learned recently that most have an internal latching system similar to the ESS and the data lines are well isolated from the clocks. Some even have internal PLL's for internal clocks that run at multiples of the master clock. its really hard to predict how different DAC's will react to jitter. I have even read of adding jitter intentionally to improve something (I forgot what). My big point was to be leery of promotional claims and get details.
Hello Ian,I think the RG 178 provides a feeling of ''greater bandwidth''more consistent in the low.I would return the clock board near the pcm board,in this case, a very short cable may be used.
Someone uses a very short cable clock?
IME, using an OCXO even on multi bit DAC (TDA1541) makes a sonic
improvement. The OP buffer will add very little phase noise if done correctly
to even a super low phase noise OCXO (Wenzel etc). One thing I have noticed
that makes a difference is the loading of the (sine wave) OCXO itself prior to
buffer and also the PS.
If I'm understanding you correctly, that appears contrary to a lot of subjective
results. Many people are preferring synchronous operation where the ASRC
is supposed to effectively 'drop out'. Do you have any direct experience with
this mode of operation on the Sabre?
WRT promotional claims - yep
WRT adding jitter intentionally, I think Antelope Audio pioneered what they
call focused jitter. It's funny, they sell a Rubidium master reference clock,
that an OCXO synchs off (presumably) that runs some form of Direct Dig
Synthesised clock.
To me that's all kind of backward but I'm guessing with the DDS makes the
addition of spectrum focussed jitter easier not to mention deriving all the
various required WC's for pro use.
Some people think they are BS, many swear by them. Obviously they
shouldn't make a difference with well designed ADC,
Terry
FIFO with PCM63 D1
Hi,
I finally have some time to try and implement the FIFO modules into a DIY replica of the D1 DAC. Before I get started, I just want to make sure that I figured out the right way to connect everything to the DAC.
The DAC is a diy version of the D1, more specifically the D1V2 from Spencer Cheung (schematics: http://www.fetaudio.com/wp-content/uploads/2009/10/BAL-PCM-63-DAC-30.pdf). The digital section consists of the following: CS8414 -> SM5847 -> 4x PCM63
If I understood correctly, first the CS8414 must be set to output a I2S signal which is done by setting the Normal audio port modes to M3=0, M2=1, M1=0, M0=0.
From there, I take the SDATA pin and connect it to the FIFO board on the SD input, the SCK to the SCK input and FSYNC to the WS input.
The FIFO board will be connected to the Si570 clock board, and the clock board to the I2S-PCM board.
Connections from the PCM board to the DAC will be done by removing the SM5847, and connecting:
- CLK to the PCM63 CLK pin,
- LLLR to the PCM63 LE pin,
- DR to the DATA pin on the first PCM63
- DRn to the DATA pin on the second PCM63
- DL to DATA on third PCM63
- DLn to DATA on the fourth PCM63
Prior to the PCM63, there's a quad OR gate (74HC86). Can the PCM board drive the PCM63 directly without having to pass by the OR gates? Given that the PCM board gives the option of having an inverted data output for a differential setup, it would simplify the connections.
Are there any disadvantages of removing the SM5847 digital filter if I connect the FIFO?
Lastly, in terms of 5V supply, can the I2S-PCM board be connected to receive its 5V from the DC 5V output (J5) on the FIFO board? If I later add the isolator board, will I have to use a completely different 5V source for the clock board and PCM board?
Paul
Hi,
I finally have some time to try and implement the FIFO modules into a DIY replica of the D1 DAC. Before I get started, I just want to make sure that I figured out the right way to connect everything to the DAC.
The DAC is a diy version of the D1, more specifically the D1V2 from Spencer Cheung (schematics: http://www.fetaudio.com/wp-content/uploads/2009/10/BAL-PCM-63-DAC-30.pdf). The digital section consists of the following: CS8414 -> SM5847 -> 4x PCM63
If I understood correctly, first the CS8414 must be set to output a I2S signal which is done by setting the Normal audio port modes to M3=0, M2=1, M1=0, M0=0.
From there, I take the SDATA pin and connect it to the FIFO board on the SD input, the SCK to the SCK input and FSYNC to the WS input.
The FIFO board will be connected to the Si570 clock board, and the clock board to the I2S-PCM board.
Connections from the PCM board to the DAC will be done by removing the SM5847, and connecting:
- CLK to the PCM63 CLK pin,
- LLLR to the PCM63 LE pin,
- DR to the DATA pin on the first PCM63
- DRn to the DATA pin on the second PCM63
- DL to DATA on third PCM63
- DLn to DATA on the fourth PCM63
Prior to the PCM63, there's a quad OR gate (74HC86). Can the PCM board drive the PCM63 directly without having to pass by the OR gates? Given that the PCM board gives the option of having an inverted data output for a differential setup, it would simplify the connections.
Are there any disadvantages of removing the SM5847 digital filter if I connect the FIFO?
Lastly, in terms of 5V supply, can the I2S-PCM board be connected to receive its 5V from the DC 5V output (J5) on the FIFO board? If I later add the isolator board, will I have to use a completely different 5V source for the clock board and PCM board?
Paul
For I2S CS8414 seems to need: M3=0, M2=0, M1=1, M0=0.
Yes
74HC86 is XOR not OR. If you are using DRn and DLn you do not need it 74HC86.
The FIFO is a "just" a FIFO, it doesn't modify the data. I2S-PCM board splits it into L, Ln and R, Rn, but still the same data.
A digital filter like SM5847 does 8x oversampling and digital filtering on the data. By removing the digital filter you will end up with a NOS (non oversampling) DAC. For a basic explanation on oversampling google for a pdf from Lavry on "Sampling, Oversampling, Imaging and Aliasing".
My 2 cents on this:
1. Leave SM5847 and use only the FIFO+clock to clean-up jitter.
2. Remove SM5847, forget about CS8414 and buy an Amanero Combo384 or similar 384MHz capable async USB thing and do the 8x upsampling on PC/ARM board
Yes for both.
Thanks for your help Vzs!
Concerning option 1 that you suggest:
From what I understand of the SM5847's datasheet, it doesn't seem to accept I2S input format. Therefore the FIFO+clock+PCM board must be inserted in-between the CS8414 and the SM5847.
To do that I would still set the CS8414 to I2S output as you've corrected, set the SM5847 to LR simultaneous, left-justified by having INF1N and INF2N high, and then connect the PCM board's DR to the SM5847's DIR and the DL to the DIL (I've attached a crudely modified schematic of the changes). Would that work?
As for your recommended option 2:
I must unfortunately still use SPDIF as input for the DAC. An option would be to use an ipod with the usb camera kit connected to the amanero and stream music to the ipod via itunes (the system must remain wife-friendly...), but I'm unsure if that would negate any benefit of going with the amanero + FIFO.
Paul
Concerning option 1 that you suggest:
From what I understand of the SM5847's datasheet, it doesn't seem to accept I2S input format. Therefore the FIFO+clock+PCM board must be inserted in-between the CS8414 and the SM5847.
To do that I would still set the CS8414 to I2S output as you've corrected, set the SM5847 to LR simultaneous, left-justified by having INF1N and INF2N high, and then connect the PCM board's DR to the SM5847's DIR and the DL to the DIL (I've attached a crudely modified schematic of the changes). Would that work?
As for your recommended option 2:
I must unfortunately still use SPDIF as input for the DAC. An option would be to use an ipod with the usb camera kit connected to the amanero and stream music to the ipod via itunes (the system must remain wife-friendly...), but I'm unsure if that would negate any benefit of going with the amanero + FIFO.
Paul
Attachments
Hi
For those looking at Ian's TPS7A4700 regs :
http://www.diyaudio.com/forums/swap-meet/254822-fs-tps7a4700-regs-iancanada-design.html
Regards
Phil
For those looking at Ian's TPS7A4700 regs :
http://www.diyaudio.com/forums/swap-meet/254822-fs-tps7a4700-regs-iancanada-design.html
Regards
Phil
@bisesik S/PDIF FIFO setup for SONY PCM7040 DAT
SONY PCM7040 DAT was one of the best broadcast grade DAT, it can be used as an great AD1865 DAC for audiophiles. You can get one with very good price from eBay now.
To run it from USB or any other SPDIF sources, you need:
1. Configure FIFO KIT as standard S/PDIF FIFO.
2. Connect the S/PDIF output to DAT7040 by either AES balanced cable or 75 ohm coaxial cable via adapter.
3. Set the panel switches as picture with "input monitor" button pressed.
Analog signals can output from both RAC and XLR connectors. But the XLR outputs have higher level than consumer audio standard. I suggest using RCA except you can figure out how to reduce the XLR level.
Ian
SONY PCM7040 DAT was one of the best broadcast grade DAT, it can be used as an great AD1865 DAC for audiophiles. You can get one with very good price from eBay now.
To run it from USB or any other SPDIF sources, you need:
1. Configure FIFO KIT as standard S/PDIF FIFO.
2. Connect the S/PDIF output to DAT7040 by either AES balanced cable or 75 ohm coaxial cable via adapter.
3. Set the panel switches as picture with "input monitor" button pressed.
Analog signals can output from both RAC and XLR connectors. But the XLR outputs have higher level than consumer audio standard. I suggest using RCA except you can figure out how to reduce the XLR level.
Ian
Attachments
Last edited: