Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

[hochopeper]

Hi Ryan,

Any chance of a photo? Is it possible that there is a problem with the i2s input cables? Or the i2s feedback cable from clock to FIFO?

I wouldn't let this project get the better of you mate, it seems obvious that there is something odd going on here as this is not the normal behaviour.


Chris

[iancanada]

Originally Posted by ryanj

Hi Ian, i tried another source, same problem.

Although if you give the Altera chip a tickle on the right side halfway up; it starts locking with the "lock" and "empty" leds flashing...

Could it be a dry solder joint?

On close inspection of the Altera chip i noticed a very small amount of solder half way up one of the legs nearly touching the leg next to it, this is the same place described above. Solder was removed, but the problem remained.

Sorry for my ignorance, this project may just defeat me! So very close though, its playing me sweet music right now.. just had to tickle it... i know its weird.

Hi ryan,

No worry about that. Send it back to me if you don't mind. I can fix it for you. I can scan the chip.

For it's lead free smt, manual re-work some times easy to get problem caused by the temperature and the material of the solder wire.

Good luck.

Ian

[ryanj]

Thanks Chris and Ian

I took a photo of the suspected problem area with a hi res camera, it reveals something suspicious. Looks like a fragment of solder in the same area where it needs a tickle to start working...

Thanks for your help guys. Either way, Ian has kindly offered to have a look at it for me if i cant fix it.

Ryan

[TNT]

Si570 interest list:

1. bigpandahk
2. tagheuer
3. hochopeper
4. qusp (of course)
5. AR2 - definitely!
6. wktk_smile
7. hirez69
8. CeeVee - you bet!
9. number9
10. analog_sa - GB maniac
11. edbk
12. atom6422
13. misterrogers X2 - Of Course!
14. NicMac - as usual!
15. Zoran
16. PET-240
17. Coolhead
18. Slartibartfasst
19. SYklab
20. Regland
21. Neb001
22. SPWONG
23. Greg Stewart (also of course!)
24. Vitalica
25. spm
26. Fridrik
27. ccliu
28. makumba1966
29. lindamar
30. Finaxe
31. Odysseas x2
32. palmito
33. crazikid
34. deanoUK
35. Julf
36. DUC985
37. rsotirov
38. kvl
39. bkdog
40. necplusultra
41. Nikola Krivorov X2
42. nvduybom
43. Popolvar
44. TNT

[tubo]

Originally Posted by TNT

Si570 interest list:

1. bigpandahk
2. tagheuer
3. hochopeper
4. qusp (of course)
5. AR2 - definitely!
6. wktk_smile
7. hirez69
8. CeeVee - you bet!
9. number9
10. analog_sa - GB maniac
11. edbk
12. atom6422
13. misterrogers X2 - Of Course!
14. NicMac - as usual!
15. Zoran
16. PET-240
17. Coolhead
18. Slartibartfasst
19. SYklab
20. Regland
21. Neb001
22. SPWONG
23. Greg Stewart (also of course!)
24. Vitalica
25. spm
26. Fridrik
27. ccliu
28. makumba1966
29. lindamar
30. Finaxe
31. Odysseas x2
32. palmito
33. crazikid
34. deanoUK
35. Julf
36. DUC985
37. rsotirov
38. kvl
39. bkdog
40. necplusultra
41. Nikola Krivorov X2
42. nvduybom
43. Popolvar
44. TNT

45. TUBO

[iancanada]

Originally Posted by iancanada

Running ESS9018 with inverted MCLK is an interesting topic. Somebody thinks it’s important, while others seems don’t much care about it. So, I did some real test on this issue with Si570 clock board V2.0 and my BIII DAC today.

Si570 prototype clock board V2.0 was configured into both normal and inverted MCLK mode. Please see the screen shoot pictures below of the waveform testing result. The white waveform is the ESS9018 MCLK running at 98.xxx MHz, the green waveform is the “eye” of I2S BCK (or SCK, WS and SD as well) signal. We can see, with normal phase MCLK configuration, changing on I2S signals follows the raising edge of MCLK. While with inverted MCLK configuration, changing on I2S signals follows the falling edge of MCLK. With the Potato 74G74 being as the re-clock FF, the delay Tpd is around 2ns and the raising/falling time is around 0.6-0.7ns. Si570 clock board was powered by an external TPS7A4700 reg PCB with a battery pack as the DC input.

The interesting thing is they really sound a bit different. But I’m not quite sure which one is better. The normal phase MCLK already sounds very good, when it turns to the inverted MCLK, feels the background a bit more quiet and dark. It’s more obvious running at 45.xxx/49.xxx MHz then at 90.xxx/98.xxx MHz. Maybe I already got familiar with the sound of normal MCLK, feels wise, the normal MCLK sounds a little bit rich. But, overall, I still think the inversed MCLK plays positive.

Based on my testing result, I think I have to include this normal/inverted MCLK feature into Si570 clock board V3.0 design. But my question is which one is better to be as the default configuration?

Ian

[qusp]

ahh hey Sorry Ian, well does it really matter which one is default? its just a setting isnt it? so can be chosen by the end user? I would say just go with Inverted since its what the datasheet calls for.

BTW its looking great and the eye diagrams are pretty interesting, thats a pretty serious scope youve bought yourself there!

[Fridrik]

Hi Ian, Any comment on the TPS7a4700 regulator? I bought the demonstration kit from TI. Will probably buy another one for the SPDIF board...

[iancanada]

Originally Posted by qusp

ahh hey Sorry Ian, well does it really matter which one is default? its just a setting isnt it? so can be chosen by the end user? I would say just go with Inverted since its what the datasheet calls for.

BTW its looking great and the eye diagrams are pretty interesting, thats a pretty serious scope youve bought yourself there!

Thanks qusp, same point as you. With inverted MCLK as default, but could jump back to normal phase MCLK. Good idea .

Ian

[Fridrik]

Very powerfull scope indeed : wife can see that her husband is working late night on special project ;-) Nov 29 22:14.


What model&Brand?